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PCM1808, System clock frequesncy in slave mode

Other Parts Discussed in Thread: PCM1808

Hello team,

I would like to know about PCM1808 system clock frequency.
I guess PCM1808 is designed for use that system clock frequency is 256fs, 384fs and 512fs, can the device accept 128fs as system clock input?
Is there internal circuitry(clock detector or clock divider) conflict and we cannot see proper operation?

Best regards,
Taketo Sato

  • Hi Taketo-san,

    This limit is likely to do with the minimum needed instruction cycles per sample that the decimation filter requires. It may be that at 128*FS the clock is not moving fast enough for the decimation filter to complete each sample. If this operation is required, I would suggest moving to the PCM186X family as it will kick in its PLL to solve this issue.

    Justin