PCM4222 PCM Quad Speed Mode

Hi Kato,

It is definitely questionable if your proposed setup would work, so i would suggest solid testing done by the customer. However, the clocks all come from the same source, and therefore I believe there is a solid chance the system will work. As you have asked, the question is how much delay through the audio processor will there be to generate LRCK, and how much can the PCM4222 handle?

Looking at our data sheet we don't specifically have this measurement. However, knowing that the data should be stable on the rising edge of BCK, and the the maximum delay from LRCK transition to data settle is 10 ns, the delay of LRCK compared to BCK should be less than BCK high low + Data delay. This means as an approximate in quad speed mode, the most delay LRCK should have is 20 ns. 20 ns + 10 ns = 30 ns, which is less than the minimum BCK HL time of 32 ns.

Justin

Hi Justin-san,

Thank you for your quick response.

The audio data interface timing is mentioned on page 51 of the PCM1860 data sheet as below.
According to your advice, is the time of "tLRSU" and "tLRHD" 32ns@Min for PCM4222 ?
So, could you please give me your advice since I would like to find out "LRCK Set up Time / Hold Time to BCK Rising Edge" for PCM4222 ?

Best regards,
Kato

Hi Justin-san,

I know you are busy, however could you please let me know "LRCK Set up Time / Hold Time to BCK Rising Edge" for PCM4222 since we should inform our customer of it ?
Your quick response would be greatly appreciated.

Best regards,
Kato

Hi Justin-san,

Thank you for your support.
Could you please look into these parameters and get back to me ?

Best regards,
Kato

Hi Justin-san,

Do you have any updates for these parameters ?

Best regards,
Kato

Hi Justin-san,

I believe that it is not reasonable for our customer if the I2S timing specification is not mentioned in the data sheet.
Could you please share reference information at least ?

Best regards,
Kato