DIR9001 FSOUT output

Hi

I'm sorry to trouble you but hope to hear from you as soon as possible.

BestRegards

Hi, na,

My colleague will take a look at this. He will answer as soon as possible.

Best regards,
Luis Fernando Rodríguez S.

Hi Na na,

1. If the PLL is unlocked, the part should be in mute.
2. When is this state happening, startup, during operation, or near an event? This is specifying that the PLL is not able to lock onto the clock from the SPDIF source, or that the counter is reading a frequency that is out of range. Are you using a 24.576 MHz crystal for the XTI source?
3. Resetting will clear the state, but it the conditions still exist the state will return.

Justin

Hi Justin

Thank you for your reply.

>1. If the PLL is unlocked, the part should be in mute.

What is the state of PLL unlocked and mute? Could you please tell us it more detail?
We can see BCLK、LRCLK、DATA output.
Could you please tell us PLL unlocked and mute more detail?

>2. When is this state happening, startup, during operation, or near an event? This is specifying that the PLL is not able to lock onto the clock from the SPDIF source, or that the counter is reading a frequency that is out of range. Are you using a 24.576 MHz crystal for the XTI source?

This state happens at startup.
Now we don't use external crystal. XTI pin are open. Is it incorrect?

>3. Resetting will clear the state, but it the conditions still exist the state will return.
How to recover the state of PLL unlocked? Do you have idea?

BestRegards

Hi

I am looking forward to hearing from you.

Thank you.

BestRegards

Hi,

1. I am not sure what you are asking for here, if the PLL is not locked, it means that the PLL cannot create a stable clock from the input clocks/data.

2.This is fine, but you wont get FSOUT information. A crystal is needed to count against the received information, so that the part can determine the audio rate. If there is no crystal then the FSOUT will likely be the out of range.

3. It will need to receive a valid SPDIF signal.

Justin

Hi Justin

Thank you for reply.

>1. I am not sure what you are asking for here, if the PLL is not locked, it means that the PLL cannot create a

>stable clock from the input clocks/data.

>2.This is fine, but you wont get FSOUT information. A crystal is needed to count against the received

>information, so that the part can determine the audio rate. If there is no crystal then the FSOUT will likely >be the out of range.

Now, we have  FSOUT1=H, FSOUT0=0 output but a crystal (24.576MHz) is not used.

If a crystal (24.576MHz) is not used, FSOUT1 and FSOUT2  have no meaning?

In other words,  FSOUT[1:0] doesn't indicate the state of PLL unlock in our case, is my understanding correct?

Additionally, if PLL operation mode would be selected, the status in the red square shown below is assumed.

In the PLL Operation mode, there is possibility the IC outputs FSOUT1=H and FSOUT0=L when startup, isn't there?

Can we judge the IC operates without error if it is used in the blue square state? (What is the meaning of "OUT"?)

And it seems to be strange that the DOUT data is MUTE(Low) in XTI operation mode with error pin "L".  We expect it would be decoded data.  Is it error?

BestRegards

Hi Justin

In addition to the above question, we made image as attached file to confirm if there is possibility to happen the following situation.

DIR9001_FSOUT.pptx

-Situation-

XTI pin : OPEN, may have noise

Sampling frequency calculator : enabled (due to noise at power on)

PLL : locked  

FSOUT[1:0]=HL (Out of range)

If XTI is open, is there possibility of FSOUT[1:0] = HL despite locked PLL?

BestRegards