TLV320DAC3120 playback tone noisy issue

Hi, Peratchi,

Welcome to E2E and thank you for your interest in our products!

When noise issues appear at the codec in some percentage of cases, it could be related with software or hardware issue. Could you provide your register configuration, please?

Additionally, I recommend to verify if your design has the following considerations:

e2e.ti.com/.../3377.common-noise-issues-in-codecs

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,


I resolved the BCLK noisy issue. But still my audio tone is playing noisy and something playing tone clearly.

Here I have mentioned the DAC register configuration details

I2CWrite(I2C_DAC_ADDR, Soft_Reset, 0x01);

// Clock Settings
I2CWrite(I2C_DAC_ADDR, Clock_Gen_Mux, 0x07);
I2CWrite(I2C_DAC_ADDR, PLL_P_R_Val, 0x94);
I2CWrite(I2C_DAC_ADDR, PLL_J_Val, 0x10);
I2CWrite(I2C_DAC_ADDR, PLL_D_MSB, 0x00);
I2CWrite(I2C_DAC_ADDR, 8,0x00);
I2CWrite(I2C_DAC_ADDR, DAC_NDAC_Val, 0x84);
I2CWrite(I2C_DAC_ADDR, DAC_MDAC_Val,0x84);
I2CWrite(I2C_DAC_ADDR, DAC_DOSR_LSB, 0x80);

// DAC Interface and Volume Control
I2CWrite(I2C_DAC_ADDR, Codec_Interface_Control, 0xc0);
I2CWrite(I2C_DAC_ADDR, DAC_DataPath_SetUp, 0xa6); // only R
I2CWrite(I2C_DAC_ADDR, DAC_Vol_Mute_Control, 0x04);
I2CWrite(I2C_DAC_ADDR, DAC_Vol_Gain_Control, 0x24);

I2CWrite(I2C_DAC_ADDR, DAC_Instruction_Set, 0x05);

I2CWrite(I2C_DAC_ADDR, Page0_Control, 0x01);

// DAC Routing and Class D SPKR Configuration
I2CWrite(I2C_DAC_ADDR, DAC_Out_Mixer_Routing, 0x40);
I2CWrite(I2C_DAC_ADDR,Analog Vol to Class-D Output Driver, 0x80);
I2CWrite(I2C_DAC_ADDR, ClassD_Spkr_Amp, 0x86);

I2CWrite(I2C_DAC_ADDR, ClassD_Out_Driver, 0x14); // Gain -18dB

I2CWrite(I2C_DAC_ADDR, Page1_Control, 0x08);

// Enabling Adaptive filter
I2CWrite(I2C_DAC_ADDR, 01, 04);




Regards
Palani.N

Hello, Palani,

Have you verified the design considerations to reduce noise issues? (e2e.ti.com/.../3377.common-noise-issues-in-codecs)

Additionally, could you provide your clock values (MCLK, BCLK, WCLK)? It is to verify if the root cause could be related with the clock settings.

Thank you.

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,

  We are not configured MCLK, Because Audio DAC is act as a slave. So We are generating BCLK=1.33MHZ from MSP430 microcontroller

  WCLK=41.6KHZ is configured below hardware counter design. ie., WCLK = BCLK / 32

Regards

Palani.N

Hi, Palani,

The noise issue should be related with the clock configuration. I recommend to configure the WCLK and sampling rate with suggested frequencies in the datasheet: 8KHz, 11.025KHz, 16KHz, 22.05KHz, 24KHz, 32KHz, 44.1KHz or 48KHz. Please ensure that the clock conditions of datasheet are respected.

Thank you.

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,

Those suggested frequencies having any +/- tolerance  level. We have tried with 8KHZ audio tone. Still I m getting noisy background with tone.

Below waveform corresponding with 32KHZ audio tones.

But We are storing the data in msp 430 buffer internally 16bit  from flash memory.

So every 16 bit We are fetching the data in msp430 and then sending with audio DAC.

So My question is .. Which WCLK frequency will consider the audio DAC device. whether 32KHZ or 23KHZ..

Regards

Palani.N

Hi Luis,

whether making both the BCLK and WCLK low after some samples . What will the consider the audio DAC in that instant.

Regards

Palani.N

Hello, Palani,

The WCLK and BCLK should be generated continuously in order to get an expected result. If there are changes in the frequencies, there could be noisy or distortion effects. Please use a continuous frequency for both clocks.

Additionally, have you tried to use different processing blocks and see if there are changes at the output? Additionally, have you tried to generate a beep to see if the noise also affects this beep tone?

Thank you.

Best regards,
Luis Fernando Rodríguez S.

Hello Lui,

Iam part of the same team. Actually We tried playing with 8KHZ sampling frequency, as the bit clock and word clock being continuously generating, but still we are seeing the noise issue. Any inputs on this.

Thanks,
Thulasiram C

Hi Luis,

  Kindly reference the attached document.

Regards

Palani.NMSP430 controller With Audio DAC Block Diagram.docx

Hi, Palani,

This should be related with the SPI as LJF I2S mode.

I have been checking your information. I noticed that the BCLK and WCLK have some differences with the timing diagram of the datasheets. In left-justified mode, BCLK falling edge must match with the WCLK rising edge as the following picture shows:

In the last captures that you sent us, it seems that your BCLK is inverted (both rising edges match). Could you try inverting the BCLK signal, please?

Thank you.

Best regards,
Luis Fernando Rodríguez S.