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Configuration of TLV320AIC3262 in Slave Mode for using DAC module only

Other Parts Discussed in Thread: TLV320AIC3262

Hi,

I am writing this mail from Guardhat Inc. We are using the TLV320AIC3262 Codec Chip for our prodcue.

We are using the TLV320AIC3262 as a slave and with our Master processor(OV788). We are using the Digital interface only.

Interfaces to TI Codec:  

- We have a MIC connected to the TI codec(GPI2 as MIC Data and GPIO2 as the MIC Clock). 

- Our Speakers are connected to the TI codec(SPKLP, SPKLM, SPKRP, SPKRM). 

- Master processor is connected to the TI Codec all the interfaces used are shown in the attached Schematic. 

We are configuring the TI codec as per below Register configurations, we expect that there should be Audio Data from MIC to be sent on the DOUT1. 

How ever we are not seeing any MIC data sent out on the DOUT1, Can you please help us check what could be wrong in the below configurations.

Aslo check the schematics attache for our design

CODEC_REG_WRITE( 0x00, 0x00);// w 30 00 00 # Initialize to Page 0

CODEC_REG_WRITE( 0x7f, 0x00);// w 30 7f 00 # Initialize to Book 0
CODEC_REG_WRITE( 0x01, 0x01);// w 30 01 01 # Initialize the device through software reset

# Delay 1 millisecond

/*configure PLL, MCLK1=24M*/
CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
CODEC_REG_WRITE( 0x04, 0x00);//w 30 04 33 # Set ADC_CLKIN = MCLK1 and DAC_CLKIN = MCLK1


CODEC_REG_WRITE( 0x00, 0x01);//w 30 00 01 # Select Page 1
CODEC_REG_WRITE( 0x01, 0x00);//w 30 01 00 # Disable weak AVDD to DVDD connection, make analog supplies available
CODEC_REG_WRITE( 0x7a, 0x01);//w 30 7a 01 # REF charging time = 40ms

// Select Page 4
CODEC_REG_WRITE( 0x00, 0x04);//w 30 00 04 # Select Page 4
CODEC_REG_WRITE( 0x01, 0x00);//w 30 01 00 # SA mode, 16-bit
CODEC_REG_WRITE( 0x0a, 0x00);//w 30 0a 00 //Dir BCK1->ASI1, WCLK->ASI1 Slave mode, BCLK and WCLK always on
CODEC_REG_WRITE( 0x08, 0xf1);//w 30 08 50 # Left Channel DAC and Primary ASI's Right channel data to Right Channel DAC
CODEC_REG_WRITE( 0x0b, 0x01);//w 30 0b 01 //BCLK source DAC_MOD_CLK=5.6448MHz
CODEC_REG_WRITE( 0x0c, 0x84);//w 30 0c 84 //BCLK DIV =4 BCLK=DAC_MOD_CLK/4
CODEC_REG_WRITE( 0x0e, 0x00);//w 30 0e 00 //BCLK Out:from ASI1BDIV ,WCLK out:use DAC_FS
CODEC_REG_WRITE( 0x10, 0x00);//w 30 10 00 //ADC WCLK is same as DAC WCLK,ADC BCLK is same as DAC BCLK (Default 4-wire Interface)
CODEC_REG_WRITE( 0x57, 0x28); // 30 57 28 // GPIO2 pin = ADC_MOD_CLK Output for digital microphone
CODEC_REG_WRITE( 0x5b, 0x00); // 30 5b 00 // GPI1 pin Disabled
CODEC_REG_WRITE( 0x5c, 0x10); // 30 5c 10 // GPI2 pin Enabled (used as Dig_Mic_In, Data for ASI1, in ClockGen block, General Purpose Input)


CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
CODEC_REG_WRITE( 0x3c, 0x01);//w 30 3c 01 # Set the DAC Mode to PRB_P1 (Setup A)


// Page 1
CODEC_REG_WRITE( 0x00, 0x01);//w 30 00 01 # Select Page 1
CODEC_REG_WRITE( 0x03, 0x00);//w 30 03 00 # Set PTM mode for Left DAC to PTM_P3 (default, writing here optional)
CODEC_REG_WRITE( 0x04, 0x00);//w 30 04 00 # Set PTM mode for Right DAC to PTM_P3 (default, writing here optional)
CODEC_REG_WRITE( 0x16, 0xe7);//w 30 16 c3 # Enable DAC to LOL/R routing and power-up LOL/R
CODEC_REG_WRITE( 0x2e, 0x00);//w 30 2E 00 # Route LOL to SPK-Left @ 0dB
CODEC_REG_WRITE( 0x2f, 0x01);//w 30 2F 00 # Route LOR to SPK-Right @ 0dB
CODEC_REG_WRITE( 0x30, 0x55);//w 30 30 11 # Set Left Speaker Gain @ 6dB, Right Speaker Gain @ 6dB
CODEC_REG_WRITE( 0x2d, 0x07);//w 30 2D 03 # Power-up Stereo Speaker
CODEC_REG_WRITE( 0x42, 0xc3);//Driver Power-Up Flags Register

// Page 0
CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
CODEC_REG_WRITE( 0x3f, 0xc0);//w 30 3f c0 # Power up the Left and Right DAC Channels
CODEC_REG_WRITE( 0x40, 0x00);//w 30 40 00 # Unmute the DAC digital volume control
CODEC_REG_WRITE( 0x25, 0x88); // Left DAC Powered Up Right DAC Powered Up

  • Hello, Ambarish,

    Welcome to E2E and thank you for your interest in our products!

    The schematic seems to be all in order. This issue should be related with the register configuration.

    Could you provide details about the clock frequencies (MCLK, BCLK, WCLK) and settings (PLL coefficients and dividers) that you are using? This is to have a better approach to this issue.

    Thank you.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi,
    Appreciate your quick response. We are using the MCLK = 24 Mhz. See below for Clock register configurations.

    /*configure PLL, MCLK1=24M*/
    CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
    CODEC_REG_WRITE( 0x04, 0x33);//w 30 04 33 # Set ADC_CLKIN = PLL_CLK and DAC_CLKIN = PLL_CLK
    CODEC_REG_WRITE( 0x05, 0x00);//w 30 05 00 # Set PLL_CLKIN = MCLK1

    CODEC_REG_WRITE( 0x06, 0x91);

    CODEC_REG_WRITE( 0x07, 0x07);
    CODEC_REG_WRITE( 0x08, 0x02);
    CODEC_REG_WRITE( 0x09, 0x30);
    CODEC_REG_WRITE( 0x0a, 0x02);
    CODEC_REG_WRITE( 0x0b, 0x83);//w 30 0b 83 //NDAC=3
    CODEC_REG_WRITE( 0x0c, 0x85);//w 30 0c 85 //MDAC=5
    CODEC_REG_WRITE( 0x0d, 0x00);
    CODEC_REG_WRITE( 0x0e, 0x80);//w 30 0d 00 80//DOSR=128

    CODEC_REG_WRITE( 0x12, 0x83);//w 30 12 83 #NADC=3 and ADC_CLK pwr
    CODEC_REG_WRITE( 0x13, 0x85);//w 30 13 85 #MADC=5, ADC_M_CLK pwr
    CODEC_REG_WRITE( 0x14, 0x80);//w 30 14 80 #AOSR=128
  • Hi, Ambarish,

    Digital microphone is enabled with book 0 / page 0 / register 81. The digital microphone pins seem to be already defined. So, you need to configure this register with the ADC that you are looking to use.

    Please let me know if you have further questions or comments.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi, Ambarish,

    Additionally, the book 0/ page 0 / register 82 should be configured to un-mute the ADCs.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi,

    Thanks for reply.

    I did try with the ADC registers you specified as well. But still I dont see any data on the DOUT1(Incoming MIC data towards our Interfacing Processor with the TI Codec)

    Let me summarize the status. I have moved the TI Codec onto Master mode back.

    Clock Configurations Used below:
    MCLK = 24Mhz
    WCLK = 44Khz
    BCLK = 1.2Mhz
    MIC CLOCK = 5.6 Mhz

    I can see that the clocks on the wire are as per above. I can see that the MIC data is coming to the TI codec.

    ----------------------------------------------------------------------------------------------------------------------------------------------
    Can you please help check if I am doing anything incorrect in the below register configurations for our design ?
    ----------------------------------------------------------------------------------------------------------------------------------------------

    ----------------------------------------------------------
    TI Codec Register Configurations are below:
    ----------------------------------------------------------
    CODEC_REG_WRITE( 0x00, 0x00);// w 30 00 00 # Initialize to Page 0
    CODEC_REG_WRITE( 0x7f, 0x00);// w 30 7f 00 # Initialize to Book 0
    CODEC_REG_WRITE( 0x01, 0x01);// w 30 01 01 # Initialize the device through software reset
    # Delay 1 millisecond

    CODEC_REG_WRITE( 0x00, 0x01);//w 30 00 01 # Select Page 1
    CODEC_REG_WRITE( 0x01, 0x00);//w 30 01 00 # Disable weak AVDD to DVDD connection, make analog supplies available
    CODEC_REG_WRITE( 0x7a, 0x01);//w 30 7a 01 # REF charging time = 40ms

    #ASI interface

    // Select Page 4
    CODEC_REG_WRITE( 0x00, 0x04);//w 30 00 04 # Select Page 4
    CODEC_REG_WRITE( 0x01, 0x00);//w 30 01 00 # SA mode, 16-bit

    CODEC_REG_WRITE( 0x57, 0x28); // 36 57 28 // GPIO2 pin = ADC_MOD_CLK Output for digital microphone
    CODEC_REG_WRITE( 0x5c, 0x10); // 36 5c 10 // GPI2 pin Enabled (used as Dig_Mic_In, Data for ASI1, in ClockGen block, Input)


    CODEC_REG_WRITE( 0x0a, 0x25);//w 30 0a 25 //Dir ASI1->BCLK1, ASI1->WCLK1 Master mode,BCLK and WCLK always on
    CODEC_REG_WRITE( 0x08, 0x50);//w 30 08 50 # Left Channel DAC and Primary ASI's Right channel data to Right Channel DAC
    CODEC_REG_WRITE( 0x0b, 0x01);//w 30 0b 01 //BCLK source DAC_MOD_CLK=5.6448MHz
    CODEC_REG_WRITE( 0x0c, 0x84);//w 30 0c 84 //BCLK DIV =4 BCLK=DAC_MOD_CLK/4
    CODEC_REG_WRITE( 0x0e, 0x00);//w 30 0e 00 //BCLK Out:from ASI1BDIV ,WCLK out:use DAC_FS
    CODEC_REG_WRITE( 0x10, 0x00);//w 30 10 00 //ADC WCLK is same as DAC WCLK,ADC BCLK is same as DAC BCLK (Default 4-wire Interface)
    CODEC_REG_WRITE( 0x05, 0x00);// 00000: All Channels of Data Input on DIN1 pin

    // Select Page 0
    CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
    CODEC_REG_WRITE( 0x51, 0xd4);// ADC Channel Power Control for enabling Mic Data input to ADC
    CODEC_REG_WRITE( 0x52, 0x00);// w 30 52 00 # Unmute ADC channel and Fine Gain = 0dB

    # Signal Processing Settings
    CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
    CODEC_REG_WRITE( 0x3c, 0x01);//w 30 3c 01 # Set the DAC Mode to PRB_P1 (Setup A)

    # Output Channel Configuration
    // Page 1
    CODEC_REG_WRITE( 0x00, 0x01);//w 30 00 01 # Select Page 1
    CODEC_REG_WRITE( 0x03, 0x00);//w 30 03 00 # Set PTM mode for Left DAC to PTM_P3 (default, writing here optional)
    CODEC_REG_WRITE( 0x04, 0x00);//w 30 04 00 # Set PTM mode for Right DAC to PTM_P3 (default, writing here optional)
    CODEC_REG_WRITE( 0x16, 0xc3);//w 30 16 c3 # Enable DAC to LOL/R routing and power-up LOL/R
    CODEC_REG_WRITE( 0x2e, 0x00);//w 30 2E 00 # Route LOL to SPK-Left @ 0dB
    CODEC_REG_WRITE( 0x2f, 0x00);//w 30 2F 00 # Route LOR to SPK-Right @ 0dB
    CODEC_REG_WRITE( 0x30, 0x11);//w 30 30 11 # Set Left Speaker Gain @ 6dB, Right Speaker Gain @ 6dB
    CODEC_REG_WRITE( 0x2d, 0x03);//w 30 2D 03 # Power-up Stereo Speaker

    // Page 0
    CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
    CODEC_REG_WRITE( 0x3f, 0xc0);//w 30 3f c0 # Power up the Left and Right DAC Channels
    CODEC_REG_WRITE( 0x40, 0x00);//w 30 40 00 # Unmute the DAC digital volume control

    /*configure PLL, MCLK1=24M*/
    CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
    CODEC_REG_WRITE( 0x04, 0x33);//w 30 04 33 # Set ADC_CLKIN = PLL_CLK and DAC_CLKIN = PLL_CLK
    CODEC_REG_WRITE( 0x05, 0x00);//w 30 05 00 # Set PLL_CLKIN = MCLK1
    CODEC_REG_WRITE( 0x06, 0x91);break;//PLLCLK=84.672M

    CODEC_REG_WRITE( 0x07, 0x07);
    CODEC_REG_WRITE( 0x08, 0x02);
    CODEC_REG_WRITE( 0x09, 0x30);
    CODEC_REG_WRITE( 0x0a, 0x02);
    CODEC_REG_WRITE( 0x0b, 0x83);//w 30 0b 83 //NDAC=3
    CODEC_REG_WRITE( 0x0c, 0x85);//w 30 0c 85 //MDAC=5
    CODEC_REG_WRITE( 0x0d, 0x00);
    CODEC_REG_WRITE( 0x0e, 0x80);//w 30 0d 00 80//DOSR=128

    CODEC_REG_WRITE( 0x12, 0x83);//w 30 12 83 #NADC=3 and ADC_CLK pwr
    CODEC_REG_WRITE( 0x13, 0x85);//w 30 13 85 #MADC=5, ADC_M_CLK pwr
    CODEC_REG_WRITE( 0x14, 0x80);//w 30 14 80 #AOSR=128
  • Hi,

    I did change the sequence of the Register configurations and see that right now the Data from TI Codec is coming to our Host Processor.
    We did a loop back in our Host processor back to the TI Codec, so that we can hear it back on the Speakers connected. We have the 8 Ohm speakers connected to the TI codec. See the schematics.

    But we can hear only a slight buzzing sound on the speaker. Since we have mic conneted, we expect the the when we speak at the MIC, we should hear back on the Speakers. Can you check with the below sequence if everything is fine ?


    ----------------------------------------------------------
    TI Codec Register Configurations are below:
    ----------------------------------------------------------
    CODEC_REG_WRITE( 0x00, 0x00);// w 30 00 00 # Initialize to Page 0
    CODEC_REG_WRITE( 0x7f, 0x00);// w 30 7f 00 # Initialize to Book 0
    CODEC_REG_WRITE( 0x01, 0x01);// w 30 01 01 # Initialize the device through software reset
    # Delay 1 millisecond

    CODEC_REG_WRITE( 0x00, 0x01);//w 30 00 01 # Select Page 1
    CODEC_REG_WRITE( 0x01, 0x00);//w 30 01 00 # Disable weak AVDD to DVDD connection, make analog supplies available
    CODEC_REG_WRITE( 0x7a, 0x01);//w 30 7a 01 # REF charging time = 40ms


    /*configure PLL, MCLK1=24M*/
    CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
    CODEC_REG_WRITE( 0x04, 0x33);//w 30 04 33 # Set ADC_CLKIN = PLL_CLK and DAC_CLKIN = PLL_CLK
    CODEC_REG_WRITE( 0x05, 0x00);//w 30 05 00 # Set PLL_CLKIN = MCLK1
    CODEC_REG_WRITE( 0x06, 0x91);break;//PLLCLK=84.672M

    CODEC_REG_WRITE( 0x07, 0x07);
    CODEC_REG_WRITE( 0x08, 0x02);
    CODEC_REG_WRITE( 0x09, 0x30);
    CODEC_REG_WRITE( 0x0a, 0x02);
    CODEC_REG_WRITE( 0x0b, 0x83);//w 30 0b 83 //NDAC=3
    CODEC_REG_WRITE( 0x0c, 0x85);//w 30 0c 85 //MDAC=5
    CODEC_REG_WRITE( 0x0d, 0x00);
    CODEC_REG_WRITE( 0x0e, 0x80);//w 30 0d 00 80//DOSR=128

    CODEC_REG_WRITE( 0x12, 0x83);//w 30 12 83 #NADC=3 and ADC_CLK pwr
    CODEC_REG_WRITE( 0x13, 0x85);//w 30 13 85 #MADC=5, ADC_M_CLK pwr
    CODEC_REG_WRITE( 0x14, 0x80);//w 30 14 80 #AOSR=128

    #ASI interface

    // Select Page 4
    CODEC_REG_WRITE( 0x00, 0x04);//w 30 00 04 # Select Page 4
    CODEC_REG_WRITE( 0x01, 0x00);//w 30 01 00 # SA mode, 16-bit

    CODEC_REG_WRITE( 0x57, 0x28); // 36 57 28 // GPIO2 pin = ADC_MOD_CLK Output for digital microphone
    CODEC_REG_WRITE( 0x5c, 0x10); // 36 5c 10 // GPI2 pin Enabled (used as Dig_Mic_In, Data for ASI1, in ClockGen block, Input)

    CODEC_REG_WRITE( 0x0a, 0x25);//w 30 0a 25 //Dir ASI1->BCLK1, ASI1->WCLK1 Master mode,BCLK and WCLK always on
    CODEC_REG_WRITE( 0x08, 0x50);//w 30 08 50 # Left Channel DAC and Primary ASI's Right channel data to Right Channel DAC
    CODEC_REG_WRITE( 0x0b, 0x01);//w 30 0b 01 //BCLK source DAC_MOD_CLK=5.6448MHz
    CODEC_REG_WRITE( 0x0c, 0x84);//w 30 0c 84 //BCLK DIV =4 BCLK=DAC_MOD_CLK/4
    CODEC_REG_WRITE( 0x0e, 0x00);//w 30 0e 00 //BCLK Out:from ASI1BDIV ,WCLK out:use DAC_FS
    CODEC_REG_WRITE( 0x10, 0x00);//w 30 10 00 //ADC WCLK is same as DAC WCLK,ADC BCLK is same as DAC BCLK (Default 4-wire Interface)
    CODEC_REG_WRITE( 0x05, 0x00);// 00000: All Channels of Data Input on DIN1 pin

    # Signal Processing Settings
    CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
    CODEC_REG_WRITE( 0x3c, 0x01);//w 30 3c 01 # Set the DAC Mode to PRB_P1 (Setup A)

    # Output Channel Configuration
    // Page 0
    CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
    CODEC_REG_WRITE( 0x3f, 0xc0);//w 30 3f c0 # Power up the Left and Right DAC Channels
    CODEC_REG_WRITE( 0x40, 0x00);//w 30 40 00 # Unmute the DAC digital volume control

    CODEC_REG_WRITE( 0x51, 0xd4);// ADC Channel Power Control for enabling Mic Data input to ADC
    CODEC_REG_WRITE( 0x52, 0x00);// w 30 52 00 # Unmute ADC channel and Fine Gain = 0dB


    // Page 1
    CODEC_REG_WRITE( 0x00, 0x01);//w 30 00 01 # Select Page 1
    CODEC_REG_WRITE( 0x03, 0x00);//w 30 03 00 # Set PTM mode for Left DAC to PTM_P3 (default, writing here optional)
    CODEC_REG_WRITE( 0x04, 0x00);//w 30 04 00 # Set PTM mode for Right DAC to PTM_P3 (default, writing here optional)
    CODEC_REG_WRITE( 0x16, 0xc3);//w 30 16 c3 # Enable DAC to LOL/R routing and power-up LOL/R
    CODEC_REG_WRITE( 0x2e, 0x00);//w 30 2E 00 # Route LOL to SPK-Left @ 0dB
    CODEC_REG_WRITE( 0x2f, 0x00);//w 30 2F 00 # Route LOR to SPK-Right @ 0dB
    CODEC_REG_WRITE( 0x30, 0x11);//w 30 30 11 # Set Left Speaker Gain @ 6dB, Right Speaker Gain @ 6dB
    CODEC_REG_WRITE( 0x2d, 0x03);//w 30 2D 03 # Power-up Stereo Speaker
  • Hi Luis Fernando Rodríguez,

    Can you please check my previous response and help me out on the register configurations ?
  • Hi, Ambarish,

    I would recommend to power up the WCLK N divider (Book 0 / Page 4 / Register 13). This divider will ensure that the WCLK is being generated correctly. Additionally, I suggest to enable external analog supplies (Book 0 / Page 1 / Register 1).

    Regarding the Class-D configuration, I recommend to take a look at this Class-D configuration example:

    Class_D_Example.txt
    #############################################
    # Speaker playback (via Line Out)
    # AVdd = 1.8V, DVdd = 1.8V, MCLK = 12.288MHz
    # PLL Disabled, DOSR = 128, PRB_P1
    # Primary I2S interface used with WCLK & BCLK as inputs to the device
    #############################################
    
    
    
    #####################################
    # Software Reset 
    #####################################
    #
    w 30 00 00
    w 30 7F 00
    w 30 01 01
    #
    ######################################
    
    
    
    ######################################
    # Clock configuration
    ######################################
    #
    # select MCLK for CODEC clock input, bypass PLL
    w 30 04 00
    #
    # NDAC = 1, MDAC = 2
    w 30 0B 81
    w 30 0C 82
    #
    # DOSR = 128
    w 30 0D 00
    w 30 0E 80
    #
    #######################################
    
    
    
    ###################################
    # Initialize the Codec
    ###################################
    #
    # select page 1
    w 30 00 01
    #
    # Disable weak connection between AVDD and DVDD
    w 30 01 00
    #
    # set the REF charging time to 40 ms
    w 30 7A 01
    #
    ##################################
    
    
    
    #######################################
    # ASI #1 configuration
    #######################################
    #
    # select page 4
    w 30 00 04
    #
    # set ASI#1 16 bits, I2S mode
    w 30 01 00
    w 30 0A 00
    #
    #########################################
    
    
    
    
    #########################################
    # Signal processing 
    #########################################
    #
    # select page 0
    w 30 00 00
    #
    # set DAC PRB mode to PRB_P1
    w 30 3C 01
    #
    ################################
    
    
    #######################################################
    # DAC configuration
    #######################################################
    #
    # select page 1
    w 30 00 01
    #
    # Set DAC PTM mode to PTM_P3
    w 30 03 00 
    w 30 04 00 
    
    #
    # Disconnect other amplifiers from LOL,LOR
    w 30 24 7f
    w 30 25 7f
    w 30 1c 7f
    w 30 1d 7f
    # LDAC to LOL, RDAC to LOR
    w 30 16 c0
    # LOL to SPKL @0dB
    w 30 2e 00
    # LOR to SPKR @0dB
    w 30 2f 00
    
    # select page 0
    w 30 00 00
    #
    # power up LDAC and RDAC
    w 30 3F C0
    #
    # select page 1
    w 30 00 01
    
    # Power up LOL, LOR
    w 30 16 c3
    # Unmute SPKL, SPKR and set each to 6dB gain
    w 30 30 41
    
    #
    #
    # select page 0
    w 30 00 00
    #
    # Unmute LDAC and RDAC volume 
    w 30 40 00
    #
    # select page 1
    w 30 00 01
    #
    # Power-up Stereo Speaker
    w 30 2d 03
    

    Best regards,
    Luis Fernando Rodríguez S.

  • Hi Luis,

    I did try this, but still see the same results. Just to be sure that our config is correct, would that be possible for you to look at our sequence of register configurations below:

    Also wanted to check with you if there is any miniDSP config that has to be done may be ?

    # Software Reset
    CODEC_REG_WRITE( 0x00, 0x00);// w 30 00 00 # Initialize to Page 0
    CODEC_REG_WRITE( 0x7f, 0x00);// w 30 7f 00 # Initialize to Book 0
    CODEC_REG_WRITE( 0x01, 0x01);// w 30 01 01 # Initialize the device through software reset

    # Delay 1 millisecond

    #Clock Config:
    // Select Page 0
    CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
    CODEC_REG_WRITE( 0x04, 0x00);// # select MCLK for CODEC clock input, bypass PLL
    CODEC_REG_WRITE( 0x0b, 0x81);//# NDAC = 1
    CODEC_REG_WRITE( 0x0c, 0x82);//# MCDAC = 2
    CODEC_REG_WRITE( 0x0d, 0x00);//# DOSR = 128
    CODEC_REG_WRITE( 0x0d, 0x80);//#

    # Power and Analog Configuration
    CODEC_REG_WRITE( 0x00, 0x01);//w 30 00 01 # Select Page 1
    CODEC_REG_WRITE( 0x01, 0x00);//w 30 01 00 # Disable weak AVDD to DVDD connection, make analog supplies available
    CODEC_REG_WRITE( 0x7a, 0x01);//w 30 7a 01 # REF charging time = 40ms

    #ASI Config
    // Select Page 4
    CODEC_REG_WRITE( 0x00, 0x04);//w 30 00 04 # Select Page 4
    CODEC_REG_WRITE( 0x01, 0x00);//w 30 01 00 # SA mode, 16-bit

    CODEC_REG_WRITE( 0x57, 0x28); // 36 57 28 // GPIO2 pin = ADC_MOD_CLK Output for digital microphone
    CODEC_REG_WRITE( 0x5c, 0x10); // 36 5c 10 // GPI2 pin Enabled (used as Dig_Mic_In, Data for ASI1, in ClockGen block, General Purpose Input)

    // ASI interface
    CODEC_REG_WRITE( 0x0a, 0x25);//w 30 0a 25 //Dir ASI1->BCLK1, ASI1->WCLK1 Master mode,BCLK and WCLK always on
    CODEC_REG_WRITE( 0x08, 0x50);//w 30 08 50 # Left Channel DAC and Primary ASI's Right channel data to Right Channel DAC
    CODEC_REG_WRITE( 0x0b, 0x01);//w 30 0b 01 //BCLK source DAC_MOD_CLK=5.6448MHz
    CODEC_REG_WRITE( 0x0c, 0x84);//w 30 0c 84 //BCLK DIV =4 BCLK=DAC_MOD_CLK/4
    CODEC_REG_WRITE( 0x0e, 0x00);//w 30 0e 00 //BCLK Out:from ASI1BDIV ,WCLK out:use DAC_FS
    CODEC_REG_WRITE( 0x10, 0x00);//w 30 10 00 //ADC WCLK is same as DAC WCLK,ADC BCLK is same as DAC BCLK (Default 4-wire Interface)
    CODEC_REG_WRITE( 0x0d, 0x01);//1: Primary WCLK N divider is powered up

    CODEC_REG_WRITE( 0x05, 0x00);// 00000: All Channels of Data Input on DIN1 pin

    # Signal Processing Settings

    CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
    CODEC_REG_WRITE( 0x3c, 0x01);//w 30 3c 01 # Set the DAC Mode to PRB_P1 (Setup A)

    # Output Channel Configuration
    // Page 1
    CODEC_REG_WRITE( 0x00, 0x01);//w 30 00 01 # Select Page 1

    CODEC_REG_WRITE( 0x03, 0x00);//w 30 03 00 # Set PTM mode for Left DAC to PTM_P3 (default, writing here optional)
    CODEC_REG_WRITE( 0x04, 0x00);//w 30 04 00 # Set PTM mode for Right DAC to PTM_P3 (default, writing here optional)

    // Disconnect other amplifiers from LOL,LOR
    CODEC_REG_WRITE( 0x24, 0x7f);// w 30 24 7f
    CODEC_REG_WRITE( 0x25, 0x7f);// w 30 25 7f
    CODEC_REG_WRITE( 0x1c, 0x7f);// w 30 1c 7f
    CODEC_REG_WRITE( 0x1d, 0x7f);// w 30 1d 7f

    // LDAC to LOL, RDAC to LOR
    CODEC_REG_WRITE( 0x16, 0xc0);//w 30 16 c3 # Enable DAC to LOL/R routing and power-up LOL/R
    CODEC_REG_WRITE( 0x2e, 0x00);//w 30 2E 00 # Route LOL to SPK-Left @ 0dB
    CODEC_REG_WRITE( 0x2f, 0x00);//w 30 2F 00 # Route LOR to SPK-Right @ 0dB

    // Page 0
    CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
    CODEC_REG_WRITE( 0x3f, 0xc0);//w 30 3f c0 # Power up the Left and Right DAC Channels


    // Page 1
    CODEC_REG_WRITE( 0x00, 0x01);//w 30 00 00 # Select Page 1
    CODEC_REG_WRITE( 0x16, 0xc3);//w 30 16 c3 # Power-up LOL/R
    CODEC_REG_WRITE( 0x30, 0x41);//w 30 30 11 # Set Left Speaker Gain @ 6dB, Right Speaker Gain @ 6dB

    // Page 0
    CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
    CODEC_REG_WRITE( 0x40, 0x00);//w 30 40 00 # Unmute the DAC digital volume control

    // Page 1
    CODEC_REG_WRITE( 0x00, 0x01);//w 30 00 00 # Select Page 1
    CODEC_REG_WRITE( 0x2d, 0x03);//w 30 2D 03 # Power-up Stereo Speaker

    // Page 0
    CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
    CODEC_REG_WRITE( 0x51, 0xd4);// ADC Channel Power Control for enabling Mic Data input to ADC
    CODEC_REG_WRITE( 0x52, 0x00);// w 30 52 00 # Unmute ADC channel and Fine Gain = 0dB
  • Hi Luis,

    We were also trying to see if there is a loopback mode within the TI codec to route the incoming MIC Data to the Speakers.
    We did configure the B0_P4_R7(010: ASI1 digital audio output data is sourced from ASI1 digital input data (ASI1-to-ASI1 loopback)).
    But we dont see any activity on the Speakers. Is this the right way to setup loop back for MIC data towards the Speaker ? Are there any other configurations to be done for routing the MIC data towards Speakers.

    We did this to:
    1. Check if we can test out the TI Codec standalone with MIC and Speaker.
    2. If this works, then we could check the configuration in TI codec for routing of MIC data towards the OV788 processor and routing of Data to Speakers coming from OV788.

    Anyways in the OV788 processor right now we are just looping back the data received from TI Codec. Ideally it should not be causing any problem here. We did monitor the data lines going to/from the OV788 and TI Codec. It seems to be looping back the received data from TI Codec.

    Let us know if you could look at the configurations in my previous post.

    Thanks for responding to our queries. Appreciate it.
  • Hello, Ambarish,

    I have few corrections in your last register configuration.

    - In order to make a correct loopback, you should route the miniDSP_A output to the miniDSP_D input. This can be made with page 4 / register 0x76. I would suggest to configure this register as 0x36.
    - You need to ensure that all the dividers of ADC side and DAC side are similar. I noticed that MADC is not equal MDAC. So, I recommend to configure MADC as 2 with page 0 / register 0x13.
    - Ensure that the sampling rate is being configured correctly. If MCLK = 24MHz, you would get a sampling rate of fs = MCLK / (NDAC * MDAC * DOSR) = 24MHz / (1 * 2 * 128) = 93.75KHz

    Please let me know if you have further questions or comments.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis,

    I got your reply on email. Dont see it in this thread though. So I am adding your reply here:

    /////////////////////////////////////////////////////////////////////////////////////////////////////////////////

    Hello, Ambarish,

    I have few corrections in your last register configuration.

    - In order to make a correct loopback, you should route the miniDSP_A output to the miniDSP_D input. This can be made with page 4 / register 0x76. I would suggest to configure this register as 0x36.

    - You need to ensure that all the dividers of ADC side and DAC side are similar. I noticed that MADC is not equal MDAC. So, I recommend to configure MADC as 2 with page 0 / register 0x13.

    - Ensure that the sampling rate is being configured correctly. If MCLK = 24MHz, you would get a sampling rate of fs = MCLK / (NDAC * MDAC * DOSR) = 24MHz / (1 * 2 * 128) = 93.75KHz

    /////////////////////////////////////////////////////////////////////////////////////////////////////////////////

    1. I will test the loopback mode and let you know.

    2. I am not sure if you looked at the Dividers for ADC and DAC. I was configuring them the same values. Please See below and it is the same in my previous posts.

    CODEC_REG_WRITE( 0x0b, 0x83);//w 30 0b 83 //NDAC=3

    CODEC_REG_WRITE( 0x0c, 0x85);//w 30 0c 85 //MDAC=5

    CODEC_REG_WRITE( 0x0d, 0x00);

    CODEC_REG_WRITE( 0x0e, 0x80);//w 30 0d 00 80//DOSR=128

    CODEC_REG_WRITE( 0x12, 0x83);//w 30 12 83 #NADC=3 and ADC_CLK pwr

    CODEC_REG_WRITE( 0x13, 0x85);//w 30 13 85 #MADC=5, ADC_M_CLK pwr

    CODEC_REG_WRITE( 0x14, 0x80);//w 30 14 80 #AOSR=128

    ------------------------------------------------------------------------------------------------------------------------

    When testing I found that the MIC we use has a max frequency of 4.8 Mhz. So I had changed the values in last few runs to eliminate that it might be causing something.  Below are our Reference Clock Configurations used:

    ------------------------------------------------------------------------------------------------------------------------

    DAC_CLKIN = 24

    ADC_CLKIN = 24

    NDAC = 1

    MDAC = 4

    OSR = 128

    NADC = 1

    MADC = 4

    AOSR = 128

    ADC_MOD_CLK = ADC_CLKIN / (1 * 4) = 6 Mhz  ---------> This is used for the MIC Clock

    DAC_FS = DAC_CLKIN / (NDAC * MDAC * DOSR) = 24/(1 * 4 * 128) = 46.875 Khz

    ADC_FS = ADC_CLKIN / (NADC * MADC * AOSR) = 24/(1 * 4 * 128) = 46.875Khz

    So with this I am able to see that the WCLK = 44 Khz and BCLK = 1.4 Mhz

    Can you please check the attachment on the exact sequence of configurations ?

    I also have a few questions to you:

    1. We are using GPIO2 as the MIC Clock. We have 2  MICs connected with one connected for transmission at Falling Edge and the other at the Rising Edge. So from the TI register configurations, we are setting register B0_P4_R101 with value 00101 (Left Channel on GPIO2 Rising Clock Edge, Right Channel on GPIO2 Falling Clock Edge). 

    Howeverifyoulook at the Table 2-4 in the same document, it says for Digital Mic Data on GPI2,  B0_P4_R101_D[4:0] can have values only 00001 or 0111x or 00111 or 01101 or 1000x. 

    Should we ignore the above statement and still configure the B0_P4_R101 register with value 00101 ?

    2. We always see that the frequency on the SPKR and SPKL is at 230 Khz ? We do see variations in the signal when Data is present for transmission on the SPKR and SPKL. See attached images.

    1. SPKR signal when Transmission is present

    2. SPKR signal when Transmission is not present

    4. Latest Configuration File for your reference. 

    # Software Reset

    CODEC_REG_WRITE( 0x00, 0x00);// w 30 00 00 # Initialize to Page 0
    CODEC_REG_WRITE( 0x7f, 0x00);// w 30 7f 00 # Initialize to Book 0
    CODEC_REG_WRITE( 0x01, 0x01);// w 30 01 01 # Initialize the device through software reset

    // d 1 # Delay 1 millisecond

    CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
    CODEC_REG_WRITE( 0x04, 0x00);// # select MCLK for CODEC clock input, bypass PLL
    CODEC_REG_WRITE( 0x0b, 0x81);//# NDAC = 1
    CODEC_REG_WRITE( 0x0c, 0x84);//# MCDAC = 4
    CODEC_REG_WRITE( 0x0d, 0x00);//# DOSR = 128
    CODEC_REG_WRITE( 0x0e, 0x80);//#

    CODEC_REG_WRITE( 0x12, 0x81); // NADC = 1
    CODEC_REG_WRITE( 0x13, 0x84); // MADC = 4
    CODEC_REG_WRITE( 0x14, 0x80); // AOSR = 128

    # Power and Analog Configuration

    CODEC_REG_WRITE( 0x00, 0x01);//w 30 00 01 # Select Page 1
    CODEC_REG_WRITE( 0x01, 0x00);//w 30 01 00 # Disable weak AVDD to DVDD connection, make analog supplies available
    CODEC_REG_WRITE( 0x7a, 0x01);//w 30 7a 01 # REF charging time = 40ms

    # Audio Serial Interface Routing Configuration - Audio Serial Interface #1

    // Select Page 4
    CODEC_REG_WRITE( 0x00, 0x04);//w 30 00 04 # Select Page 4
    CODEC_REG_WRITE( 0x01, 0x00);//w 30 01 00 # SA mode, 16-bit

    CODEC_REG_WRITE( 0x57, 0x28); // 36 57 28 // GPIO2 pin = ADC_MOD_CLK Output for digital microphone
    CODEC_REG_WRITE( 0x5b, 0x00); // GPI1 Disabled
    CODEC_REG_WRITE( 0x5c, 0x10); // 36 5c 10 // GPI2 pin Enabled (used as Dig_Mic_In, Data for ASI1, in ClockGen block, General Purpose Input)
    CODEC_REG_WRITE( 0x60, 0x00); // 36 5c 10 // GPIO1 disabled

    CODEC_REG_WRITE( 0x65, 0x05); // Microphone data on GPIO2 clock 00101: Left Channel on GPIO2 Rising Clock Edge, Right Channel on GPIO2 Falling Clock Edge

    CODEC_REG_WRITE( 0x0a, 0x25);//w 30 0a 25 //Dir ASI1->BCLK1, ASI1->WCLK1 Master mode,BCLK and WCLK always on
    CODEC_REG_WRITE( 0x08, 0x50);//w 30 08 50 # Left Channel DAC and Primary ASI's Right channel data to Right Channel DAC
    CODEC_REG_WRITE( 0x0b, 0x01);//w 30 0b 01 //BCLK source DAC_MOD_CLK=5.6448MHz
    CODEC_REG_WRITE( 0x0c, 0x84);//w 30 0c 84 //BCLK DIV =4 BCLK=DAC_MOD_CLK/4
    CODEC_REG_WRITE( 0x0d, 0xa0);//1: Primary WCLK N divider is powered up
    CODEC_REG_WRITE( 0x0e, 0x02);//w 30 0e 00 //BCLK Out:from ASI1BDIV ,WCLK out:use DAC_FS
    CODEC_REG_WRITE( 0x10, 0x00);//w 30 10 00 //ADC WCLK is same as DAC WCLK,ADC BCLK is same as DAC BCLK (Default 4-wire Interface)

    CODEC_REG_WRITE( 0x05, 0x00);// 00000: All Channels of Data Input on DIN1 pin


    # Signal Processing Settings

    CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
    CODEC_REG_WRITE( 0x3c, 0x01);//w 30 3c 01 # Set the DAC Mode to PRB_P1 (Setup A)

    # Output Channel Configuration
    ####################################################################################*/

    // Page 1
    CODEC_REG_WRITE( 0x00, 0x01);//w 30 00 01 # Select Page 1
    CODEC_REG_WRITE( 0x03, 0x00);//w 30 03 00 # Set PTM mode for Left DAC to PTM_P3 (default, writing here optional)
    CODEC_REG_WRITE( 0x04, 0x00);//w 30 04 00 # Set PTM mode for Right DAC to PTM_P3 (default, writing here optional)

    // Disconnect other amplifiers from LOL,LOR
    CODEC_REG_WRITE( 0x24, 0x7f);// w 30 24 7f
    CODEC_REG_WRITE( 0x25, 0x7f);// w 30 25 7f
    CODEC_REG_WRITE( 0x1c, 0x7f);// w 30 1c 7f
    CODEC_REG_WRITE( 0x1d, 0x7f);// w 30 1d 7f

    // LDAC to LOL, RDAC to LOR
    CODEC_REG_WRITE( 0x2e, 0x00);//w 30 2E 00 # Route LOL to SPK-Left @ 0dB
    CODEC_REG_WRITE( 0x2f, 0x00);//w 30 2F 00 # Route LOR to SPK-Right @ 0dB

    // Page 0
    CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
    CODEC_REG_WRITE( 0x3f, 0xc0);//w 30 3f c0 # Power up the Left and Right DAC Channels

    // Page 1
    CODEC_REG_WRITE( 0x00, 0x01);//w 30 00 01 # Select Page 1
    CODEC_REG_WRITE( 0x16, 0xc3);//w 30 16 c3 # Power-up LOL/R
    CODEC_REG_WRITE( 0x30, 0x11);//w 30 30 11 # Set Left Speaker Gain @ 6dB, Right Speaker Gain @ 6dB

    // Page 0
    CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
    CODEC_REG_WRITE( 0x40, 0x00);//w 30 40 00 # Unmute the DAC digital volume control

    // Page 1
    CODEC_REG_WRITE( 0x00, 0x01);//w 30 00 01 # Select Page 1
    CODEC_REG_WRITE( 0x2d, 0x03);//w 30 2D 03 # Power-up Stereo Speaker

    // Page 0
    CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
    CODEC_REG_WRITE( 0x51, 0xd4);// ADC Channel Power Control for enabling Mic Data input to ADC
    CODEC_REG_WRITE( 0x52, 0x00);// w 30 52 00 # Unmute ADC channel and Fine Gain = 0dB

    CODEC_REG_WRITE( 0x41, 0x30);//LDAC volume
    CODEC_REG_WRITE( 0x42, 0x30);//RDAC volume

  • Hello, Ambarish,

    I verified your last register configuration. Please see the responses to your answers below:

    1. Table 2-4 explains which register configuration is used to configure the GPI2 as digital microphone input. The options that you mentioned (00001 or 0111x or 00111 or 01101 or 1000x) configure the GPI2 as microphone data. So, I would recommend to configure B0_P4_R101 as 0000 0001.

    2. The variations in the SPK output are made when there's data being taken from the DAC. When there's only a 243KHz square-wave, it means that there's no data being taken or the Class-D speaker is muted.

    The playback and recording section are configured correctly. So, I recommend to check the digital microphone connections and configuration to ensure that it is all in order. I recommend to use the loopback function to verify the digital mic function.

    Best regards,
    Luis Fernando Rodríguez S.