Hi,
I am writing this mail from Guardhat Inc. We are using the TLV320AIC3262 Codec Chip for our prodcue.
We are using the TLV320AIC3262 as a slave and with our Master processor(OV788). We are using the Digital interface only.
Interfaces to TI Codec:
- We have a MIC connected to the TI codec(GPI2 as MIC Data and GPIO2 as the MIC Clock).
- Our Speakers are connected to the TI codec(SPKLP, SPKLM, SPKRP, SPKRM).
- Master processor is connected to the TI Codec all the interfaces used are shown in the attached Schematic.
We are configuring the TI codec as per below Register configurations, we expect that there should be Audio Data from MIC to be sent on the DOUT1.
How ever we are not seeing any MIC data sent out on the DOUT1, Can you please help us check what could be wrong in the below configurations.
Aslo check the schematics attache for our design
CODEC_REG_WRITE( 0x00, 0x00);// w 30 00 00 # Initialize to Page 0
CODEC_REG_WRITE( 0x7f, 0x00);// w 30 7f 00 # Initialize to Book 0
CODEC_REG_WRITE( 0x01, 0x01);// w 30 01 01 # Initialize the device through software reset
# Delay 1 millisecond
/*configure PLL, MCLK1=24M*/
CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
CODEC_REG_WRITE( 0x04, 0x00);//w 30 04 33 # Set ADC_CLKIN = MCLK1 and DAC_CLKIN = MCLK1
CODEC_REG_WRITE( 0x00, 0x01);//w 30 00 01 # Select Page 1
CODEC_REG_WRITE( 0x01, 0x00);//w 30 01 00 # Disable weak AVDD to DVDD connection, make analog supplies available
CODEC_REG_WRITE( 0x7a, 0x01);//w 30 7a 01 # REF charging time = 40ms
// Select Page 4
CODEC_REG_WRITE( 0x00, 0x04);//w 30 00 04 # Select Page 4
CODEC_REG_WRITE( 0x01, 0x00);//w 30 01 00 # SA mode, 16-bit
CODEC_REG_WRITE( 0x0a, 0x00);//w 30 0a 00 //Dir BCK1->ASI1, WCLK->ASI1 Slave mode, BCLK and WCLK always on
CODEC_REG_WRITE( 0x08, 0xf1);//w 30 08 50 # Left Channel DAC and Primary ASI's Right channel data to Right Channel DAC
CODEC_REG_WRITE( 0x0b, 0x01);//w 30 0b 01 //BCLK source DAC_MOD_CLK=5.6448MHz
CODEC_REG_WRITE( 0x0c, 0x84);//w 30 0c 84 //BCLK DIV =4 BCLK=DAC_MOD_CLK/4
CODEC_REG_WRITE( 0x0e, 0x00);//w 30 0e 00 //BCLK Out:from ASI1BDIV ,WCLK out:use DAC_FS
CODEC_REG_WRITE( 0x10, 0x00);//w 30 10 00 //ADC WCLK is same as DAC WCLK,ADC BCLK is same as DAC BCLK (Default 4-wire Interface)
CODEC_REG_WRITE( 0x57, 0x28); // 30 57 28 // GPIO2 pin = ADC_MOD_CLK Output for digital microphone
CODEC_REG_WRITE( 0x5b, 0x00); // 30 5b 00 // GPI1 pin Disabled
CODEC_REG_WRITE( 0x5c, 0x10); // 30 5c 10 // GPI2 pin Enabled (used as Dig_Mic_In, Data for ASI1, in ClockGen block, General Purpose Input)
CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
CODEC_REG_WRITE( 0x3c, 0x01);//w 30 3c 01 # Set the DAC Mode to PRB_P1 (Setup A)
// Page 1
CODEC_REG_WRITE( 0x00, 0x01);//w 30 00 01 # Select Page 1
CODEC_REG_WRITE( 0x03, 0x00);//w 30 03 00 # Set PTM mode for Left DAC to PTM_P3 (default, writing here optional)
CODEC_REG_WRITE( 0x04, 0x00);//w 30 04 00 # Set PTM mode for Right DAC to PTM_P3 (default, writing here optional)
CODEC_REG_WRITE( 0x16, 0xe7);//w 30 16 c3 # Enable DAC to LOL/R routing and power-up LOL/R
CODEC_REG_WRITE( 0x2e, 0x00);//w 30 2E 00 # Route LOL to SPK-Left @ 0dB
CODEC_REG_WRITE( 0x2f, 0x01);//w 30 2F 00 # Route LOR to SPK-Right @ 0dB
CODEC_REG_WRITE( 0x30, 0x55);//w 30 30 11 # Set Left Speaker Gain @ 6dB, Right Speaker Gain @ 6dB
CODEC_REG_WRITE( 0x2d, 0x07);//w 30 2D 03 # Power-up Stereo Speaker
CODEC_REG_WRITE( 0x42, 0xc3);//Driver Power-Up Flags Register
// Page 0
CODEC_REG_WRITE( 0x00, 0x00);//w 30 00 00 # Select Page 0
CODEC_REG_WRITE( 0x3f, 0xc0);//w 30 3f c0 # Power up the Left and Right DAC Channels
CODEC_REG_WRITE( 0x40, 0x00);//w 30 40 00 # Unmute the DAC digital volume control
CODEC_REG_WRITE( 0x25, 0x88); // Left DAC Powered Up Right DAC Powered Up