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TLV320DAC3203 digital microphone (PDM) to Headphone output

Other Parts Discussed in Thread: TLV320DAC3203

Hello Everyone

I try to implement an audio function which needs to combine digital microphone (PDM) input and music input (INL/INR) to headphone output (HPL & HPR). And TLV320DAC3203 is chosen to do the combination. I am new with this Codec, currently I am able to output music input to headphone, but have big trouble to output digital microphone (PDM) to Headphone output. From the user guide, I got the data flow should be as the following:

PDM in --> ADC --> DSP --> Audio Interface --> DAC --> HP

So I  came out configuration as the following,  and cannot hear the sound of digital microphone from the headphone, please help, thanks.

{0x00, 0x00}, // 0. Initialize to page 0
{0x01, 0x01}, // 1. Initialize the device through software reset
{0x04, 0x03}, // 2. Set PLL_CLKIN as MCLK and CODEC_CLKIN as PLL_CLK
{0x05, 0x93}, // 3. Power up pll, set pll divider P=1 and pll divider R=3
{0x06, 0x07}, // 4. Set pll divider J=7
{0x07, 0x00}, // 5. Set pll divider D=0000
{0x08, 0x00}, // 6.
{0x12, 0x87}, // 7. Power up and set NADC divider = 7
{0x13, 0x89}, // 8. Power up and set MDAC divider = 9
{0x14, 0x40}, // 9. Set AOSR = 64
{0x1b, 0x40}, // 10. Set the word length of audio interface to 16 bits, audio interface to DSP
{0x3c, 0x01}, // 11. Set the DAC mode to PRB_P1
{0x00, 0x01}, // 12. Select page 1
{0x01, 0x08}, // 13. Disable internal crude AVdd in presence of external AVdd supply
{0x02, 0x00}, // 14. Enable master analog power control
{0x7b, 0x01}, // 15. Set the REF charging time to 40ms
{0x0a, 0x00}, // 16. Set the input common mode to 0.9V and output common mode for headphone to input common mode
{0x0c, 0x0c}, // 17. Route left DAC & INL to HPL
{0x0d, 0x0c}, // 18. Route right DAC & INR to HPR
{0x03, 0x00}, // 19. Set the DAC PTM mode to PTM_P3
{0x04, 0x00}, // 20.
{0x10, 0x00}, // 21. Set the HPL gain to 0dB
{0x11, 0x00}, // 22. Set the HPR gain to 0dB
{0x14, 0x29}, // 23. HP soft stepping settings for optimal pop performance at power up. Rpop used is 6k with N = 6 & soft step = 20usec
{0x09, 0x30}, // 24. Power up HPL and HPR drivers
{0x00, 0x00}, // 25. Select page 0
{0x41, 0x00}, // 26. Set the left DAC digital volume control to 0 dB
{0x42, 0x00}, // 27. Set the right DAC digital volume control to 0 dB
{0x3f, 0xd6}, // 28. Power up left and right DAC channel, routing left and right audio interface
{0x40, 0x00}, // 29. Unmute the DAC digital volume control
{0x37, 0x0e}, // 30. Configure MISO as clock output for digital microphone
{0x51, 0xdc}, // 31. Power up left ADC and right ADC. Enable digital microphone mode for left ADC and right ADC. Treat data on SCLK as digital microphone data
{0x52, 0x00}};// 32. Unmute left ADC and right ADC

  • Hi, Joy,

    Welcome to E2E and thank you for your interest in our products!

    It would be necessary to make a loopback to get the PDM data with the DAC. So, I recommend to enable the loopback control with Page 0 / Register 29. If this doesn't work, could you try routing the DOUT pin to the DIN pin?

    Additionally, could you provide the clock frequencies values? (MCLK, BCLK, WCLK). Finally, are you getting a clock signal at the MISO pin and the DOUT pin?

    Thank you.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis

    Thanks a lot for the information. 

    After configure Page 0 / Register 29 to enable the loopback function, it's still not working.

    And when you said "routing the DOUT pin to the DIN pin", do you mean to physically connect these 2 pins? Because I am not able to find any related register to do the routing.

    The clock frequencies values are MCLK: 4MHz, BCLK: 1.027MHz, MISO: 1.076MHz. But I failed to get clock signals on WCLK & DOUT.

    For WCLK, I have configured Page 0 / Register 27 to 0x0d, Page 0 / Register 29 to 0x24, Page 0 / Register 32 & 33 to reset values, and set CDIV_CLKIN = BULK and power up and set CLKOUT M divider = 1 

    Currently I am using pin 6, DMDIN, & pin 9, DMCLK/MISO, as digital microphone (PDM) pins.

    Thank you so much for your time.

    BR,

    Joy Fan

  • Hi, Joy,

    Yes, I was referring to connect the DOUT pin to the DIN pin.

    I have additional questions about your application. Are you configuring the device in Master mode (BCLK and WCLK as outputs, generated by the codec) or Slave mode (BCLK and WCLK as inputs, generated by an external device)? What is the sampling frequency that you expect to use in your application (this should be the same than the WCLK)?

    Have you modified your first registers code? It seems that register 29 is not configured in your first code.

    Thank you.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis

    The device is configured as Master mode, BCLK and WCLK as output, and I expect to have 16KHz sampling frequency on both DAC_fs and ADC_fs based on CODEC_CLKIN 112MHz, NADC/NDAC 2, MADC/MDAC 52, AOSR/DOSR  64.

    And yes, I have modified my register code as the following, you can find register 29 / 0x01d on line 13.

    {0x00, 0x00}, // 0. Initialize to page 0
    {0x01, 0x01}, // 1. Initialize the device through software reset
    {0x04, 0x03}, // 2. Set PLL_CLKIN as MCLK and CODEC_CLKIN as PLL_CLK
    {0x05, 0x94}, // 3. Power up pll, set pll divider P=1 and pll divider R=4
    {0x06, 0x07}, // 4. Set pll divider J=7
    {0x07, 0x00}, // 5. Set pll divider D=0000
    {0x08, 0x00}, // 6.
    {0x12, 0x82}, // 7. Power up and set NADC divider = 2
    {0x13, 0xb4}, // 8. Power up and set MDAC divider = 52
    {0x14, 0x40}, // 9. Set AOSR = 64
    {0x0b, 0x82}, // 10. Power up and set NDAC divider = 2
    {0x0c, 0xb4}, // 11. Power up and set MDAC divider = 52
    {0x0d, 0x40}, // 12. Set DOSR = 64
    {0x1d, 0x24}, // 13. Enable loopback, BDIV_CLKIN = DAC_CLK
    {0x1e, 0xb6}, // 14. Power up and set BCLK N divider = 54
    {0x19, 0x03}, // 15. CDIV_CLKIN = PLL_CLK
    {0x1a, 0xed}, // 16. Power up and set CLKOUT M divider = 109
    {0x21, 0x03}, // 17.
    {0x1b, 0x0d}, // 18. Set the word length of audio interface to 16 bits, audio interface to I2S
    {0x3c, 0x01}, // 19. Set the DAC mode to PRB_P1
    {0x00, 0x01}, // 20. Select page 1
    {0x01, 0x08}, // 21. Disable internal crude AVdd in presence of external AVdd supply
    {0x02, 0x00}, // 22. Enable master analog power control
    {0x7b, 0x01}, // 23. Set the REF charging time to 40ms
    {0x0a, 0x00}, // 24. Set the input common mode to 0.9V and output common mode for headphone to input common mode
    {0x0c, 0x0c}, // 25. Route left DAC & INL to HPL
    {0x0d, 0x0c}, // 26. Route right DAC & INR to HPR
    {0x03, 0x00}, // 27. Set the DAC PTM mode to PTM_P3
    {0x04, 0x00}, // 28.
    {0x10, 0x00}, // 29. Set the HPL gain to 0dB
    {0x11, 0x00}, // 30. Set the HPR gain to 0dB
    {0x14, 0x29}, // 31. HP soft stepping settings for optimal pop performance at power up. Rpop used is 6k with N = 6 & soft step = 20usec
    {0x09, 0x30}, // 32. Power up HPL and HPR drivers
    {0x00, 0x00}, // 33. Select page 0
    {0x37, 0x0e}, // 34. Configure MISO as clock output for digital microphone
    {0x51, 0xdc}, // 35. Power up left ADC and right ADC. Enable digital microphone mode for left ADC and right ADC. Treat data on DIN as digital microphone data
    {0x52, 0x00}, // 36. Unmute left ADC and right ADC
    {0x41, 0x00}, // 37. Set the left DAC digital volume control to 0 dB
    {0x42, 0x00}, // 38. Set the right DAC digital volume control to 0 dB
    {0x3f, 0xd6}, // 39. Power up left and right DAC channel, routing left and right audio interface
    {0x40, 0x00} // 40. Unmute the DAC digital volume control

    BR,

    Joy Fan

  • Hi, Joy,

    This should be related with the clock settings. In order to get a better performance and the correct clock configuration, I recommend to try with the following values:

    R = 4; J = 32; P = 5
    NDAC = NADC = 5
    MDAC = MADC = 10
    AOSR = DOSR = 128

    These values would give a CODEC_CLKIN = 102.4MHz; DAC_CLK = ADC_CLK = 20.480 MHz; DIG_MIC_CLK = 2.048MHz.

    Please let me know if the problem persists.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis

    Thank you for the information.

    I was able to have the PDM output to headphone by the following settings:

    •Configure I2S as master mode, BLCK & WCLK as output
    •Connect DIN & DOUT
    •Set loopback function as disabled
    Thanks again for your tips which gave me directions to figure out this setting.
    BR,
    Joy