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using SRC4382 to transfer data command

The customer want to transfer data command through S/PDIF. They find register 0x16 has the function of  receiver buffer transfer interrupt, but don't know which register should be used to write and read data.

In the datasheet, I find maybe User data bit could be used to transfer the data command. DIR and DIT will be saved in Page 1 and Page 2 respectively. Is that correct?

And would you please provide example code to realize this function? Thank you.

  • Hi, Robin,

    As mentioned in Register and Data Buffer Organization section, Register Page 2 contains the digital interface transmitter channel status and user data buffers. The contents of these buffers correspond to the data contained in the C and U bits of the transmitted data stream and they may be written through the SPI or I2C serial host interface to configure the C and U bits.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis,

    Thanks for your reply. Could you please share example code which could be used to realize this function?

    Robin Yu

  • Hi, Robin,

    In order to configure this function, it is necessary to configure the following registers:

    Register 08 (Transmitter Control Register 2) / Bit TXBTD should be '1' to allow the user to update DIT C and U data buffers.
    Register 09 (Transmitter Control Register 3) / Bits TXCUS[1:0] should be "01" to update the buffers via SPI or I2C.
    Register Page 02 are used to write the DIT User Data Buffer Map.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis,

    The customer has tried as below:

    They use two machines, one for S/PDIF transmitter, the other for receiver. Both the sound of  transmitted and received are OK.

    Write data at transmitter terminal, and check the interrupt register at receiver terminal. No data could be received.

    Now it is a very urgent case for the customer. Attached is the Language C code, please check.

    Could you please check the code(initialization and read data code)?

    Thank you.

    Robin

    SRC4382.c
    // choose port B output source��reg 0x05
    #define PORT_MASTER_IIS             0x09
    #define PORT_SLAVE_IIS			0x01
    
    #define PORT_SOURCE_PORTB           (0<<4)
    #define PORT_SOURCE_PORTA           (1<<4)
    #define PORT_SOURCE_DIR             (2<<4)
    #define PORT_SOURCE_SRC             (3<<4)
    
    // port B Master Mode Clock Divider, reg 0x06
    #define PORT_CLOCK_DIV_MASK         0x03
    #define PORT_CLOCK_DIV_128          0
    #define PORT_CLOCK_DIV_256          1
    #define PORT_CLOCK_DIV_384          2
    #define PORT_CLOCK_DIV_512          3
    
    #define PORT_CLOCK_SOURCE_MASK      (0x03<<2)
    #define PORT_CLOCK_SOURCE_MCLK      (0x00<<2)
    #define PORT_CLOCK_SOURCE_RXCKI     (0x01<<2)
    #define PORT_CLOCK_SOURCE_RXCKO     (0x02<<2)
    
    // TX config reg1, reg 0x07
    #define TX_CLOCK_MASK               (0x01<<7)
    #define TX_CLOCK_MCLK               (0x00<<7)
    #define TX_CLOCK_RXCKO              (0x01<<7)
    
    #define TX_CLOCK_DIV_MASK           (0x03<<5)
    #define TX_CLOCK_DIV_128            (0x00<<5)
    #define TX_CLOCK_DIV_256            (0x01<<5)
    #define TX_CLOCK_DIV_384            (0x02<<5)
    #define TX_CLOCK_DIV_512            (0x03<<5)
    
    #define TX_SOURCE_MASK              (0x03<<3)
    #define TX_SOURCE_PORTA             (0x00<<3)
    #define TX_SOURCE_PORTB             (0x01<<3)
    #define TX_SOURCE_DIR               (0x02<<3)
    #define TX_SOURCE_SRC               (0x03<<3)
    
    // reg 0x08 tx bypass
    #define TX_BYPASS_RX1               (0x00|0x30)
    #define TX_BYPASS_RX2               (0x40|0x30)
    #define TX_BYPASS_RX3               (0x80|0x30)
    #define TX_BYPASS_RX4               (0xC0|0x30)
    
    #define TXBTD					(0x01<<3)
    
    // Reg 0x0A SRC and DIT Read Status
    #define TBTI						0x01
    
    //Reg 0x0B SRC and DIT Int mask
    #define MTBI_MASK				(0x01<<0)
    
    //Reg 0x0C SRC and DIT Int mode
    #define TBTIM_RISING_ACTIVE	(0x00<<0)
    #define TBTIM_FALLING_ACTIVE	(0x01<<0)
    #define TBTIM_LEVEL_ACTIVE		(0x02<<0)
    
    
    // reg 0x0d
    #define DIR_RX_1                    0x00
    #define DIR_RX_2                    0x01
    #define DIR_RX_3                    0x02
    #define DIR_RX_4                    0x03
    
    #define RXBTD				(0x01 << 4)
    
    // reg 0x16 Rec buf transfer int
    #define MRBTI_MASK					(0x01 << 0)
    
    // reg 0x18 Rev Int Active Reg
    #define RBTIM_RISING_ACTIVE		(0x00 << 0)
    #define RBTIM_FALLING_ACTIVE		(0x01 << 0)
    
    
    // reg 0x2d
    #define SRC_SOURCE_MASK             0x03
    #define SRC_SOURCE_PORTA            0
    #define SRC_SOURCE_PORTB            1
    #define SRC_SOURCE_DIR              2
    
    #define SRC_CLOCK_SOURCE_MASK       (0x03<<2)
    #define SRC_CLOCK_SOURCE_MCLK       (0x00<<2)
    #define SRC_CLOCK_SOURCE_RXCKI      (0x01<<2)
    #define SRC_CLOCK_SOURCE_RXCKO      (0x02<<2)
    
    
    
    // reg 0x7F Page Selection Register
    #define PAGE0_MASK				(0x00 << 0)
    #define PAGE1_MASK				(0x01 << 0) //DIR
    #define PAGE2_MASK				(0x02 << 0)  //DIT
    
    
    
    /*****************************  Only Read Register ******************************/
    #define GLOBAL_INT_STATUS_REG			0x02
    #define SRC_INT				0x01
    #define RX_INT				0x02
    #define TX_INT				0x04
    
    
    #define SRC_DIT_STATUS_REG		0x0A
    
    
    #define REV_STAUTS_REG1		0x13
    #define REV_STAUTS_REG2		0x14
    #define REV_STAUTS_REG3		0x15
    
    // Reg 0x14 Receiver Read Status
    #define RBTI_INT						0x01
    
    
    #define DIR_USER_DATA_ADDR		0x40
    #define DIT_USER_DATA_ADDR		0x40
    
    
    void Audio_SRC4382_Init (void)
    {
    	SRC4382_MSG("init\r\n");
    
    	SRC_RST_L;
    	delayms(100);
    	SRC_RST_H;
    	delayms(100);
    
    	SRC_MUTE_L;
    
    	SRC4382Write (0x7F, PAGE0_MASK);    // Page 1
    	
    	SRC4382_PUTC (0x01, 0x3F); //Power-Down and reset (Disable power down)
    
    	SRC4382Write (0x03, 0x21);    // DIR to port A 24bit IIS, Slave
    	SRC4382Write (0x05, 0x29);    // DIR to port B , 24bit IIS, Master 
    
    	//Mclk=24.576Mhz  Div=256  LRCK=96Khz
    	reg06 = PORT_CLOCK_DIV_256 | PORT_CLOCK_SOURCE_MCLK;
    	SRC4382Write (0x06, reg06); //PortB Master config (Only for master mode)
    	SRC4382Write (0x04, (PORT_CLOCK_DIV_256 | PORT_CLOCK_SOURCE_MCLK));    // PortA Master config (Only for master mode)
    
    	reg07 = TX_CLOCK_MCLK | TX_CLOCK_DIV_256 | TX_SOURCE_SRC;
    	SRC4382Write (0x07, reg07);
    
    	//Transfer config
    	SRC4382Write (0x08, TXBTD| 0x00); //Transmitter Control Register
    //	SRC4382Write (0x09, 0x03); //Transmitter Control Register3(10 bytes of the buffers are update)
    	SRC4382Write (0x09, 0x01); //Transmitter Control Register1(the buffers are update)
    //	SRC4382Write (0x0B, MTBI_MASK); //Transmitter Buf init enable
    //	SRC4382Write (0x0C, TBTIM_FALLING_ACTIVE); //Transmitter Buf init mode falling edge active
    	
    	//Receive config
    	SRC4382Write (0x0D, DIR_RX_2 | RXBTD | 0x08); //Receiver Control Register1
    	SRC4382Write (0x0E, 0x01);//Receiver Control Register2
    	SRC4382Write (0x16, MRBTI_MASK);		//Rec buffer transfer Interruput Maks Reg
    	SRC4382Write (0x18, RBTIM_FALLING_ACTIVE);		//Rec buffer transfer Interruput Maks Reg
    
    	SRC4382Write (0x0F, 0x22);    // P = 2
    	SRC4382Write (0x10, 0x00);    // J = 8
    	SRC4382Write (0x11, 0x00);    // D = 0   		(P:2 J:8 D:0)Clock Rate:24.576MHz
    
    	reg2d = SRC_SOURCE_DIR| SRC_CLOCK_SOURCE_MCLK;
    	SRC4382Write (0x2D, reg2d); //SRC Control Reg 1
    
    	SRC4382Write (0x2E, 0x00); //SRC Ctol Reg 2
    }
    
    void Audio_SRC4382_Rev_DIR(void)
    {
    #if 1
    	U8 Rev_Status;
    	
    	SRC4382Write (0x7F, PAGE0_MASK);    // Page 0
    	Rev_Status = SRC4382_GETC(GLOBAL_INT_STATUS_REG);
    	SRC4382_MSG("Global Int: 0x%x\r\n", Rev_Status);
    	if (Rev_Status & RX_INT)
    	{
    		Rev_Status = SRC4382_GETC(REV_STAUTS_REG2);
    		SRC4382_MSG("Rev Int: 0x%x\r\n", Rev_Status);
    		if (Rev_Status & RBTI_INT)
    		{
    			SRC4382Write (0x7F, PAGE1_MASK);    // Page 1
    			Rev_Status = SRC4382_GETC(DIR_USER_DATA_ADDR);
    			SRC4382_MSG("Rev Data: 0x%x\r\n", Rev_Status);
    			SRC4382Write (0x7F, PAGE0_MASK);    // Page 0
    		}
    	}
    #endif
    }
    
    void Audio_SRC4382_Wr_DIT(void)
    {
    #if 1
    	SRC4382Write (0x7F, PAGE2_MASK);    // Page 2
    	SRC4382Write (DIT_USER_DATA_ADDR, 0xa5);
    	SRC4382Write (0x7F, PAGE0_MASK);    // Page 0
    	SRC4382_MSG("Wr Data 0xa5 to Reg0x40\r\n");
    #endif
    }