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BCLK oddity using a AIC3254 with only MCLK

Terry Newton
Prodigy 50 points
Other Parts Discussed in Thread: TLV320AIC3254

Hello,

Background - I'm using a AIC3254 configured as a simple audio preamp/processor. The design consists of a 11.2896mhz oscillator connected to MCLK (the other clock inputs are not connected), a small PIC microcontroller that transfers code from an eeprom to the '3254 via I2C, serial/programming ports for downloading the code and not much else. The idea was to make something that could run code produced by PurePath for a '3254-U EVM as-is with no changes besides scripted conversions to convert the .cfg file into the format I used for eeprom storage (strip comments whitespace etc but otherwise still the same script). On boot the PIC reads code from the eeprom one w30xxyy.. sequence at a time and sends it to the '3254 (including interpreting w30fexx as a millisecond delay). The MCLK oscillator runs all the time. The circuit is built on perfboard using an adapter board for the '3254 - bad I know but for testing I don't care about noise, just want to get the design right before committing to foil.

All that stuff works fine, with serial debug functions I can dump the '3254 registers and it matches the script values. Except it doesn't work. Here's the odd thing and the question - discovered that if I touched the BCLK pin it suddenly came to life and worked fine, and was surprisingly quiet considering the way it was built. Further discovered that to get it working without human digit intervention I had to connect BCLK to anything that oscillated for a bit (doesn't have to continue oscillating), I have an LED that flashes while booting so used that. Here's the really strange part - needed a 100K resistor in series with BCLK. Direct connection or a 470 ohm resistor did not work. I'm glad it works, but I'm puzzled as to why I need to do anything with BCLK at all, and especially puzzled about needing a series resistor.

First question is why? Has anyone heard of anything like this? Possibly due to the poor layout using the DIP adapter?

Next question is what is the proper way to treat MCLK and the clock inputs I don't need?

Sorry for the mystery :-) but I'd kind of like to figure out the observed behavior before moving forward with the design, thanks for any insights.

  • 0
    TI__Guru* 84915 points
    Hi, Terry,

    Our TLV320AIC32xx devices have processing blocks and some of them have programmable miniDSP. When the device is configured in slave mode (BCLK and WCLK as inputs), it is necessary to send several pulses by the BCLK in order to get the processing blocks / miniDSP initialized. In case of master mode (BCLK and WCLK as outputs), the codec will generate the BCLK and WCLK, so it is just necessary to ensure that there are signals at these pins. Basically, we recommend to have the BCLK and WCLK clocks enabled to get the TLV320AIC3254 fully configured.

    Please let me know if you have additional questions or comments.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 50 points

    Thanks for the reply, it confirms my suspicion that BCLK is required to initialize. Is this documented anywhere? How many pulses? when? Why does applying pulses to the BCLK pin (in the form of 60hz stray) make it start working even though in my config the BCLK pin is disabled? This is a simple audio in/out app, all internal clocks are derived from the single MCLK input. Although my workaround worked yesterday it is unreliable today, it could still simply be because of too much trace length from the chip to the decoupling caps (the adapter), still before doing the real layout I need to know how to properly initialize and which pins need connecting... from what I'm gathering so far I need a pin from my processor to BCLK with a series resistor in case that pin is configured as an out. Source code for the firmware in the '3254EVM-U module would help a lot. Thanks.

  • 0 in reply to Terry Newton
    TI__Guru* 84915 points
    Hi, Terry,

    This behavior was observed during testing and we don't have a documentation about this. Based on our tests, it was necessary around 8 BCLK pulses to get the codec properly initialized. So, we recommend to have a BCLK signal when this pin is configured as input or configure this pin as output and enable ADC/DAC with the BDIV divider enabled.

    Best regards,
    Luis Fernando Rodríguez S.