PCM4222: Timing Information for Input Data Sampling

Sadanori Kato

Part Number: PCM4222

Hi,

Could you please share us the information at time before being sampled after inputting the master clock(MCLKI) ?
Our condition is shown as below.
For instance, PCM186x is mentioned in the data sheet as below.

<Condition>
- DSD Master Mode
- 64 x Output Mode
- MCLK = 4 x fdsd

Best regards,
Kato

over 7 years ago

0 Diego Melendez over 7 years ago

TI__Guru 57800 points

Hi, Kato-san,

We will take a look to your question, could you please clarify the timing parameter you are looking for?

Best Regards,

-Diego Meléndez López
Audio Applications Engineer

0 Sadanori Kato over 7 years ago in reply to Diego Melendez

Guru 36490 points

Hi Diego-san,

Thank you for your response.
Please see the following timing information.
Could you please share me the information about "Time to Start Sampling" ?

Best regards,
Kato

0 Diego Melendez over 7 years ago in reply to Sadanori Kato

TI__Guru 57800 points

Hi, Kato-san,

Thanks for the clarification. It might take some time to get this data. This parameter could be estimated by using an EVM while monitoring the DSDCLK. I don't have an EVM at hand but will check if I can get one to measure this.

Best Regards,

-Diego Meléndez López
Audio Applications Engineer

0 Sadanori Kato over 7 years ago in reply to Diego Melendez

Guru 36490 points

Hi Diego-san,

Thank you for your reply.
I also don't have an EVM at hand, so could you please measure this ?

Best regards,
Kato

0 Sadanori Kato over 7 years ago in reply to Sadanori Kato

Guru 36490 points

Hi Diego-san,

Could you please let us know if you have any updates on my question ?

Best regards,
Kato

0 Sadanori Kato over 7 years ago in reply to Sadanori Kato

Guru 36490 points

Hi Diego-san,

Do you have any updates on my question ?

Best regards,
Kato

0 Diego Melendez over 7 years ago in reply to Sadanori Kato

TI__Guru 57800 points

Hi, Kato-san,

I just received the EVM and performed some tests. It seems that DSD clock operation starts after the internal reset process is complete. I will try to perform further testing and will get back to you in the next couple of days.

Best Regards,

-Diego Meléndez López
Audio Applications Engineer

0 Sadanori Kato over 7 years ago in reply to Diego Melendez

Guru 36490 points

Hi Diego-san,

Thank you for your special support.
I am looking forward to getting the information from you.

Best regards,
Kato

0 Sadanori Kato over 7 years ago in reply to Sadanori Kato

Guru 36490 points

Hi Diego-san,

Please let me know if you have any updates on my question.

Best regards,
Kato

0 Sadanori Kato over 7 years ago in reply to Sadanori Kato

Guru 36490 points

Hi Diego-san,

Do you have any updates on my question ?

Best regards,
Kato

0 Diego Melendez over 7 years ago in reply to Sadanori Kato

TI__Guru 57800 points

Hi, Kato-san,

Sorry for the delay. After further testing the timing seems like the same, DSD clock operation starts after the internal reset process is complete.

Best Regards,

-Diego Meléndez López
Audio Applications Engineer

0 Sadanori Kato over 7 years ago in reply to Diego Melendez

Guru 36490 points

Hi Diego-san,

Thank you for your support.

Could you please summarize the results which you measured and share the material to me since I would like to grasp the timing for the first sampling ?

Best regards,
Kato

0 Sadanori Kato over 7 years ago in reply to Sadanori Kato

Guru 36490 points

Hi Diego-san,

Please let me know if you have any updates on this question since I should inform our customer of that information.

Best regards,
Kato

0 Sadanori Kato over 7 years ago in reply to Sadanori Kato

Guru 36490 points

Hi Diego-san,

Please let me know if you have any updates on my question ?

Best regards,
Kato

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PCM4222: Timing Information for Input Data Sampling