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TLV320AIC3100: MIC_PGA ADC Gain Output

Part Number: TLV320AIC3100

Hi,

We have a circuit where we use the codec in combination with a mems mic as seen below.

The Problem we have now is that the analog gain of the ADC input (page 1/reg 47) is showing a  strange behavior we tested this on the evaluation module as well.

The picture below shows the gradual increase of the PGA register from 0 to 59,5dB.

And the steps zoomed in show a drop of 6dB when for example changing 17,5dB to 18dB. Those are all the same step changed multiple times to check for constant behavior.

Any ideas about this?

Rgds

Simon

  • Hi, Simon,

    Welcome to E2E and thank you for your interest in our products!

    Could you provide the register configuration, please? This is to have a better approach to this issue.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi, 

    I did a registry dump from page 0-8 I guess all the needed registers are in there.

    reg dump.txt
    --------------Page 0------------ 
     
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    shell> 
    shell> getcodec 0 60 10
    --------------Page 0------------ 
     
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    shell> 
    shell> getcodec 0 110 10
    --------------Page 0------------ 
     
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    shell> 
    shell> getcodec 1 60 10
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    shell> 
    shell> getcodec 2 120 10
    --------------Page 2------------ 
     
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    shell> 
    shell> getcodec 3 50 10
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    shell> 
    shell> getcodec 3 60 10
    --------------Page 3------------ 
     
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    shell> 
    shell> getcodec 5 40 10
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    shell> 
    shell> getcodec 5 100 10
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     41	0x00 
     42	0x00 
     43	0x00 
     44	0x00 
     45	0x00 
     46	0x00 
     47	0x00 
     48	0x00 
     49	0x00 
    --------------Page 6------------ 
     
     Reg	Data 
     50	0x00 
     51	0x00 
     52	0x00 
     53	0x00 
     54	0x00 
     55	0x00 
     56	0x00 
     57	0x00 
     58	0x00 
     59	0x00 
    --------------Page 6------------ 
     
     Reg	Data 
     60	0x00 
     61	0x00 
     62	0x00 
     63	0x00 
     64	0x00 
     65	0x00 
     66	0x00 
     67	0x00 
     68	0x00 
     69	0x00 
    --------------Page 6------------ 
     
     Reg	Data 
     70	0x00 
     71	0x00 
     72	0x00 
     73	0x00 
     74	0x00 
     75	0x00 
     76	0x00 
     77	0x00 
     78	0x00 
     79	0x00 
    --------------Page 6------------ 
     
     Reg	Data 
     80	0x00 
     81	0x00 
     82	0x00 
     83	0x00 
     84	0x00 
     85	0x00 
     86	0x00 
     87	0x00 
     88	0x00 
     89	0x00 
    --------------Page 6------------ 
     
     Reg	Data 
     90	0x00 
     91	0x00 
     92	0x00 
     93	0x00 
     94	0x00 
     95	0x00 
     96	0x00 
     97	0x00 
     98	0x00 
     99	0x00 
    --------------Page 6------------ 
     
     Reg	Data 
     100	0x00 
     101	0x00 
     102	0x00 
     103	0x00 
     104	0x00 
     105	0x00 
     106	0x00 
     107	0x00 
     108	0x00 
     109	0x00 
    --------------Page 6------------ 
     
     Reg	Data 
     110	0x00 
     111	0x00 
     112	0x00 
     113	0x00 
     114	0x00 
     115	0x00 
     116	0x00 
     117	0x00 
     118	0x00 
     119	0x00 
    --------------Page 6------------ 
     
     Reg	Data 
     120	0x00 
     121	0x00 
     122	0x00 
     123	0x00 
     124	0x00 
     125	0x00 
     126	0x00 
     127	0x00 
    --------------Page 7------------ 
     
     Reg	Data 
     0	0x07 
     1	0x00 
     2	0x00 
     3	0x00 
     4	0x00 
     5	0x00 
     6	0x00 
     7	0x00 
     8	0x00 
     9	0x00 
    --------------Page 7------------ 
     
     Reg	Data 
     10	0x00 
     11	0x00 
     12	0x00 
     13	0x00 
     14	0x00 
     15	0x00 
     16	0x00 
     17	0x00 
     18	0x00 
     19	0x00 
    --------------Page 7------------ 
     
     Reg	Data 
     20	0x00 
     21	0x00 
     22	0x00 
     23	0x00 
     24	0x00 
     25	0x00 
     26	0x00 
     27	0x00 
     28	0x00 
     29	0x00 
    --------------Page 7------------ 
     
     Reg	Data 
     30	0x00 
     31	0x00 
     32	0x00 
     33	0x00 
     34	0x00 
     35	0x00 
     36	0x00 
     37	0x00 
     38	0x00 
     39	0x00 
    --------------Page 7------------ 
     
     Reg	Data 
     40	0x00 
     41	0x00 
     42	0x00 
     43	0x00 
     44	0x00 
     45	0x00 
     46	0x00 
     47	0x00 
     48	0x00 
     49	0x00 
    --------------Page 7------------ 
     
     Reg	Data 
     50	0x00 
     51	0x00 
     52	0x00 
     53	0x00 
     54	0x00 
     55	0x00 
     56	0x00 
     57	0x00 
     58	0x00 
     59	0x00 
    --------------Page 7------------ 
     
     Reg	Data 
     60	0x00 
     61	0x00 
     62	0x00 
     63	0x00 
     64	0x00 
     65	0x00 
     66	0x00 
     67	0x00 
     68	0x00 
     69	0x00 
    --------------Page 7------------ 
     
     Reg	Data 
     70	0x00 
     71	0x00 
     72	0x00 
     73	0x00 
     74	0x00 
     75	0x00 
     76	0x00 
     77	0x00 
     78	0x00 
     79	0x00 
    --------------Page 7------------ 
     
     Reg	Data 
     80	0x00 
     81	0x00 
     82	0x00 
     83	0x00 
     84	0x00 
     85	0x00 
     86	0x00 
     87	0x00 
     88	0x00 
     89	0x00 
    --------------Page 7------------ 
     
     Reg	Data 
     90	0x00 
     91	0x00 
     92	0x00 
     93	0x00 
     94	0x00 
     95	0x00 
     96	0x00 
     97	0x00 
     98	0x00 
     99	0x00 
    --------------Page 7------------ 
     
     Reg	Data 
     100	0x00 
     101	0x00 
     102	0x00 
     103	0x00 
     104	0x00 
     105	0x00 
     106	0x00 
     107	0x00 
     108	0x00 
     109	0x00 
    --------------Page 7------------ 
     
     Reg	Data 
     110	0x00 
     111	0x00 
     112	0x00 
     113	0x00 
     114	0x00 
     115	0x00 
     116	0x00 
     117	0x00 
     118	0x00 
     119	0x00 
    --------------Page 7------------ 
     
     Reg	Data 
     120	0x00 
     121	0x00 
     122	0x00 
     123	0x00 
     124	0x00 
     125	0x00 
     126	0x00 
     127	0x00 
    --------------Page 8------------ 
     
     Reg	Data 
     0	0x08 
     1	0x06 
     2	0x1e 
     3	0x5f 
     4	0x1e 
     5	0x5f 
     6	0x1e 
     7	0x5f 
     8	0x0e 
     9	0xd5 
    --------------Page 8------------ 
     
     Reg	Data 
     10	0xe8 
     11	0xd5 
     12	0x7d 
     13	0xcf 
     14	0x82 
     15	0x31 
     16	0x7d 
     17	0xcf 
     18	0x7d 
     19	0xca 
    --------------Page 8------------ 
     
     Reg	Data 
     20	0x84 
     21	0x57 
     22	0x7f 
     23	0xff 
     24	0x00 
     25	0x00 
     26	0x00 
     27	0x00 
     28	0x00 
     29	0x00 
    --------------Page 8------------ 
     
     Reg	Data 
     30	0x00 
     31	0x00 
     32	0x7f 
     33	0xff 
     34	0x00 
     35	0x00 
     36	0x00 
     37	0x00 
     38	0x00 
     39	0x00 
    --------------Page 8------------ 
     
     Reg	Data 
     40	0x00 
     41	0x00 
     42	0x7f 
     43	0xff 
     44	0x00 
     45	0x00 
     46	0x00 
     47	0x00 
     48	0x00 
     49	0x00 
    --------------Page 8------------ 
     
     Reg	Data 
     50	0x00 
     51	0x00 
     52	0x7f 
     53	0xff 
     54	0x00 
     55	0x00 
     56	0x00 
     57	0x00 
     58	0x00 
     59	0x00 
    --------------Page 8------------ 
     
     Reg	Data 
     60	0x00 
     61	0x00 
     62	0x00 
     63	0x00 
     64	0x00 
     65	0x00 
     66	0x1e 
     67	0x5f 
     68	0x1e 
     69	0x5f 
    --------------Page 8------------ 
     
     Reg	Data 
     70	0x1e 
     71	0x5f 
     72	0x0e 
     73	0xd5 
     74	0xe8 
     75	0xd5 
     76	0x7d 
     77	0xcf 
     78	0x82 
     79	0x31 
    shell> 
    shell> getcodec 8 80 10
    --------------Page 8------------ 
     
     Reg	Data 
     80	0x7d 
     81	0xcf 
     82	0x7d 
     83	0xca 
     84	0x84 
     85	0x57 
     86	0x7f 
     87	0xff 
     88	0x00 
     89	0x00 
    --------------Page 8------------ 
     
     Reg	Data 
     90	0x00 
     91	0x00 
     92	0x00 
     93	0x00 
     94	0x00 
     95	0x00 
     96	0x7f 
     97	0xff 
     98	0x00 
     99	0x00 
    --------------Page 8------------ 
     
     Reg	Data 
     100	0x00 
     101	0x00 
     102	0x00 
     103	0x00 
     104	0x00 
     105	0x00 
     106	0x7f 
     107	0xff 
     108	0x00 
     109	0x00 
    --------------Page 8------------ 
     
     Reg	Data 
     110	0x00 
     111	0x00 
     112	0x00 
     113	0x00 
     114	0x00 
     115	0x00 
     116	0x7f 
     117	0xff 
     118	0x00 
     119	0x00 
    --------------Page 8------------ 
     
     Reg	Data 
     120	0x00 
     121	0x00 
     122	0x00 
     123	0x00 
     124	0x00 
     125	0x00 
     126	0x00 
     127	0x00 

    Rgds

    Simon

  • Hi, Simon,

    This seems to be related with a clock settings issue. Could you also provide the MCLK, BCLK and WCLK frequency values, please?

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi,

    I hope so, that would be easy to fix. I tried different clock setting but none of them seemed to fix this.
    MCLK = 12,288MHz
    BCLK = 1,024MHz
    WCLK = 32kHz

    Rgds
    Simon
  • Hi, Simon,

    Page 0 / Register 20 (ADC AOSR_VAL) seems to be configured as AOSR = 256 (0000 0000). You would require an AOSR = 128. Could you configure this register as 0x80? This will correctly configure the AOSR value to get 32KHz sampling rate.

    Please let me know if the problem persists.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi,

    I changed the AOSR register and it does not seem to help. As soon as I change the register I get a around 40dB less at the ADC input which makes it really hard to measure the behavior but from what I have seen I still have the same some steps in the gain.

    Something strange that I also want to point out is that I cannot set the filters for the ADC on page 4 after my initialization and also as soon as I set the clocks and enable the ADC all the filter registers are set to 0. As we don't use them it not problem for us but maybe there is some kind of a connection there.

    Rgds

    Simon

  • So, just to be sure I double checked my clock settings. As I wrote before the AOSR does not solve my gain problem and also seems to dampen my signal.

    As you can see we have the same behavior as I have shown in my first post.

    Just to be sure I measured the clocks in the codec over the muxing on the GPIO1 pin:

    Divider  M 128
    MCLK 96.1 12.3E+6
    BCLK 8 1.0E+6
    DAC CLK 96.1 12.3E+6
    DAC MOD CLK 32.2 4.1E+6
    ADC CLK 96.1 12.3E+6
    ADC MOD CLK 32.2 4.1E+6

    Rgds

    Simon

  • Hi, Simon,

    Thank you for provide the clock settings.

    In past posts you mentioned that the clock values are:

    MCLK = 12,288MHz
    BCLK = 1,024MHz
    WCLK = 32kHz

    Is this correct? The measured values don't seem to be according to these ones.

    Also, you need to ensure that the maximum clock frequencies are respected. In the provided values, they don't seem to respect the clock frequencies:

    www.ti.com/.../tlv320aic3100.pdf

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi,

    I think the measured values are in tolerance of the measurement accuracy. I put the values in a table for better readability.

    Name Calculated Measured Limit
    MCLK 12,288MHz 12,3MHz ≤ 110 MHz (CODEC_CLKIN)
    BCLK 1,024MHz 1MHz ≤ 14,3 MHz (according datasheet 3.4.2)
    DAC CLK 12,288MHz 12,3MHz ≤ 49.152 MHz
    DAC MOD CLK 4,1MHz 4,1MHz 6.758 MHz
    ADC CLK 12,288MHz 12,3MHz ≤ 49.152 MHz
    ADC MOD CLK 4,1MHz 4,1MHz 6.758 MHz
    DAC_fs 32kHz NA 0,192 MHz
    ADC_fs 32kHz NA 0,192 MHz
    WCLK 32kHz 32kHz NA

    I hope this table is easier to understand as the other one was more notes for me but I thought it would help.

    Rgds

    Simon

  • Hi, Simon,

    The problem seems to be related to the AOSR value. It is being configured as 256. Could you configure Page 0 / Register 20 as 0x80?

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi 

    yes I have changed AOSR, unfortunately that doesn't solve my problem with the ADC_PGA. We have an input of -40dBm and the gain of 36dB in the register setting is 4dB measured. From 36 to 59,5dB the register curve is correct which leads to a measured maximum gain of 28dB. And with AOSR  set to 0x80 we also have an ugly noise at 8,8kHz. Is there a init script that would work with your TLV320DAC3100EVM at 32kHz? I already have the binary loaded but the provided "Codec Control Software" doesn't seem to be able to init the codec correctly.

    Rgds

    Simon

  • Hi, Simon,

    First of all, I recommend to verify that the EVM is configured to work at 32KHz. You may verify this with the WCLK. WCLK frequency must be 32KHz.

    Then, take a look at the attached script. It contains a registers initialization for 32KHz sampling rate.

    Init_script.txt
    #			--------------------------------------------------------------- page 0 is selected 
    w 30 00 00
    #			 s/w reset
    > 01
    #			 PLL_clkin = MCLK,codec_clkin = MCLK
    w 30 04 00
    #			 mode is i2s,wordlength is 16
    w 30 1b 00
    #			 NDAC is powered up and set to 1
    w 30 0b 81
    #			 MDAC is powered up and set to 3
    > 83
    w 30 0e 80
    #			  
    w 30 74 00
    #			 DAC => drc disable, th and hy
    w 30 44 00
    #			 DAC => 0 db gain left
    w 30 41 00
    #			 DAC => 0 db gain right
    > 00
    #			--------------------------------------------------------------- page 1 is selected
    w 30 00 01
    #			 De-pop, Power on = 800 ms, Step time = 4 ms
    w 30 21 4e
    #			 HPL and HPR powered up
    w 30 1f c2
    #			 LDAC routed to HPL, RDAC routed to HPR
    w 30 23 88
    #			 HPL unmute and gain 1db
    w 30 28 0e
    #			 HPR unmute and gain 1db
    > 0e
    #			 No attenuation on HP
    w 30 24 00
    w 30 25 00
    
    #			 MIC BIAS = AVDD
    w 30 2e 0b
    #
    #			--------------------------------------------------------------- page 0 is selected
    w 30 00 00
    #			 select DAC DSP mode 11 & enable adaptive filter
    w 30 3c 0b
    w 30 00 08
    w 30 01 04
    w 30 00 00
    #			 POWERUP DAC left and right channels (soft step disable)
    w 30 3f d6
    #			 UNMUTE DAC left and right channels
    > 00
    w 30 00 01
    #			DAC_L and DAC_R are routed to mixer amplifier
    w 30 23 44
    #			Left Analog Volume to SPK
    w 30 26 80
    #			Class-D Speaker Driver unmuted
    w 30 2a 04
    #			Power-up Class-D driver
    w 30 20 c6
    #			Left DAC channel to HPL		
    w 30 24 00
    #			Right DAC channel to HPR
    w 30 25 00
    #			HPL driver unmuted
    w 30 28 04
    #			HPR driver unmuted
    w 30 29 04
    #			HPL and HPR powered up
    w 30 1f c2

    Best regards,
    Luis Fernando Rodríguez S.

  • Hi,

    I checked the WCLK and we have 32kHz. unfortunately your script seems to be incomplete as the ADC relevant blocks are not initialized. I manually set the relevant register after running your script wich leads to same result/problem as i have mentioned in my posts before. Could you please provide a initialization of the ADC->I2S path at 32kHz? 

    Rgds

    Simon

  • Hi, Simon,

    Please take a look at the attached script. It contains the ADC -> I2S path initialization at 32KHz.

    Init_script_II.txt
    #			--------------------------------------------------------------- page 0 is selected 
    w 30 00 00
    #			 s/w reset
    > 01
    #			 PLL_clkin = MCLK,codec_clkin = MCLK
    w 30 04 00
    #			 mode is i2s,wordlength is 16
    w 30 1b 00
    #			 NDAC is powered up and set to 1
    w 30 0b 81
    #			 MDAC is powered up and set to 3
    > 83
    w 30 0e 80
    #			 NADC is powered up and set to 1
    w 30 12 81
    #			 MADC is powered up and set to 3
    > 83
    > 80
    #			  
    w 30 74 00
    #			 DAC => drc disable, th and hy
    w 30 44 00
    #			 DAC => 0 db gain left
    w 30 41 00
    #			 DAC => 0 db gain right
    > 00
    #			--------------------------------------------------------------- page 1 is selected
    w 30 00 01
    #			 De-pop, Power on = 800 ms, Step time = 4 ms
    w 30 21 4e
    #			 HPL and HPR powered up
    w 30 1f c2
    #			 LDAC routed to HPL, RDAC routed to HPR
    w 30 23 88
    #			 HPL unmute and gain 1db
    w 30 28 0e
    #			 HPR unmute and gain 1db
    > 0e
    #			 No attenuation on HP
    w 30 24 00
    w 30 25 00
    
    #			 MIC BIAS = AVDD
    w 30 2e 0b
    #			 MICPGA P = MIC 10k
    w 30 30 40
    #			 MICPGA M - CM 10k
    > 40
    #			--------------------------------------------------------------- page 0 is selected
    w 30 00 00
    #			 select DAC DSP mode 11 & enable adaptive filter
    w 30 3c 0b
    #			 POWERUP ADC channel
    w 30 51 80
    #			 UNMUTE ADC channel
    > 00
    #                       --------------------------------------------------------------- page 8
    w 30 00 08
    w 30 01 04
    #                       --------------------------------------------------------------- page 0
    w 30 00 00
    #			 POWERUP DAC left and right channels (soft step disable)
    w 30 3f d6
    #			 UNMUTE DAC left and right channels
    > 00
    w 30 00 01
    #			DAC_L and DAC_R are routed to mixer amplifier
    w 30 23 44
    #			Left Analog Volume to SPK
    w 30 26 80
    #			Class-D Speaker Driver unmuted
    w 30 2a 04
    #			Power-up Class-D driver
    w 30 20 c6
    #			Left DAC channel to HPL		
    w 30 24 00
    #			Right DAC channel to HPR
    w 30 25 00
    #			HPL driver unmuted
    w 30 28 04
    #			HPR driver unmuted
    w 30 29 04
    #			HPL and HPR powered up
    w 30 1f c2

    Best regards,
    Luis Fernando Rodríguez S.

  • Hi,

    Thanks for the fast reply. I already checked it on the EVM board and it still has the same behavior. I have to change three registers for our setup where we have the microphone connected to MIC1RP. The changed registers are Page 1/Reg 48: 0x20/Reg 49: 0x00. I also have to adjust the analog mic gain Page 1/Reg 47: 0x00-0x77.

    I am running out of ideas what the reason could be. As I am testing it on the EVM Board it shouldn't be a hardware problem and the microphone seems to deliver a strong enough signal.

    Rgds
    Simon
  • Hi, Simon,

    Could you try using a line input to test the EVM? I mean, could you make a test sending an audio signal from the PC headphone/line output to the MIC-IN input of the EVM? I tested this on my EVM with a sampling rate of 32KHz and I am getting correct results.

    Please use the script that I provided for this test and let me know your results.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi,

    So it seems to work with a direkt signal feed which is kind of strange but at least I know now where to look. I will try to improve the microphone input and check if the BIAS is working correctly.

    Thanks for your help

    Rgds

    Simon