PCM1865: PLL does not lock, is not selected as clock

ClearFlowingDream

Part Number: PCM1865

Hi,

we've been trying to get the PLL to work for some time now and making 0 progress.

Here's the register settings.

Running...

PG 0 REG 0xB: 0x45
PG 0 REG 0xC: 0x0
PG 0 REG 0xD: 0x0
PG 0 REG 0x20: data=0x5E clkdet_en=0 adc_clk_src=1 mst_mode=1 mst_sck_src=0
PG 0 REG 0x25: 0x7
PG 0 REG 0x26: 0x3
PG 0 REG 0x27: data=0x3F div=1/64 DEFAULT
PG 0 REG 0x28: data=0x1 lock=0 pll en=1 DEFAULT
PG 0 REG 0x29: P=1/3
PG 0 REG 0x2A: R=1/2
PG 0 REG 0x2B: J=5
PG 0 REG 0x2C: D[7:0]=0x16
PG 0 REG 0x2D: D[13:8]=0x23
PG 0 REG 0x36: 0x0
PG 0 REG 0x70: data=0x0 digital_stby=0 sleep=0 pwrdn=0 DEFAULT
PG 0 REG 0x71: 0x10
PG 0 REG 0x72: current device state: Run
PG 0 REG 0x73: =0x4: 88.2-96kHz
PG 0 REG 0x74: =0x32: SCK_RATIO=256 BCK_RATIO=64
PG 0 REG 0x75: 0x0
PG 0 REG 0x78: 0x7
PG 3 REG 0x12: 0x40

-- PLL not locked. Reg 0x28 is 0x1

The reference clock is 25MHz and as you can see from the pictures, we are simply seeing divided down 25MHz as BCK and LRCK. I would assume that even if the PLL is not locked, we would see the divided down (incorrect) frequency of the PLL. But that's not happening either.

Any ideas ?

Thanks,

Brian

over 7 years ago

0 Diego Melendez over 7 years ago

TI__Guru 57800 points

Hi, Brian,

I made a review of the code you provided and have a couple comments.

ADC, DSP1 and DSP2 clock dividers are not configured.
R should not be different than 1 when D≠0000, this is not meeting the specs for a correct PLL operation.

I generated the following coefficients according to your settings, I haven't tried them in an EVM but plan to make it on Monday. Please let me know if this helps.

Fs=48KHz
BCLK=64×Fs
MCK=25MHz

PLL_CLKIN=MCK

P=3
R=1
J=11
D=7965

PLL_DIV=1/8
MCK_DIV=1/4
BCK_DIV=1/64

DSP1_DIV=1/8
DSP2_DIV=1/8
DSP1_DIV=1/16

Best Regards,

-Diego Meléndez López
Audio Applications Engineer

0 ClearFlowingDream over 7 years ago

Prodigy 60 points

Thank you for your response.

We tried the new values, and we still see the same issue, i.e. a divided down 25MHz - the PLL is not being selected.

The PLL lock bit gets set, so that's good.

I just recently obtained the PCM1865 eval board, so we will definitely give the eval board a try on Monday.

Brian

0 Diego Melendez over 7 years ago in reply to ClearFlowingDream

TI__Guru 57800 points

Hi, Brian,

Thanks for the feedback. I just figured out the main issue, you need to configure PLL_CLK as the Master mode Clock source. This is done by setting bit B5 of register 32 (0x20) to '1'. In current datasheet there is a typo where instead of PLL, the text mentions BCK . We are correcting this in the next datasheet release.

Best Regards,

-Diego Meléndez López
Audio Applications Engineer

0 ClearFlowingDream over 7 years ago in reply to Diego Melendez

Prodigy 60 points

That indeed was the problem.

It turns out that we also had issues with the PLL calculations due to my confusion over the actual register value vs the P/R value used in the calculations.

So now we see the PLL output and things all make sense.

Thanks Diego!

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PCM1865: PLL does not lock, is not selected as clock