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TLV320AIC3101: Register Settings for Loopback

Part Number: TLV320AIC3101

Hello,

I am developing with two TLV320AIC3101 and I am trying to do a loopback test between the two. On the input/master chip I send an analog signal to LINE2L/R and output to DOUT. I then pass WCLK/BCLK and the data to DIN on the output/slave chip. I then output the analog signal on LEFT_LOM/P and RIGHT_LOM/P however, all I hear is static on the output.

Could you please take a look at the register settings I have attached and advise if I am using the correct settings so I can determine if my problem lies with the register settings or something else (hardware related).

Thank you for your time.

Register_Settings.txt
Register	Value		Note	

1		0x80		software reset
4		0x0C		J = 3
5		0x05		D value (set WCLK = 48kHZ, MCLK = 27MHz)
6		0x06		D value

Input/Master Chip:
19		0x7C		power up adc
22		0x7C		power up adc
8		0xE0		set master
15		0x00		enable pga-adc
16		0x00		enable pga-adc
17		0x0F		enable LINE2L
18		0xF0		enable LINE2R

Output/Slave Chip
7		0x0A		DAC set stereo, dual rate mode off
14		0x40		Stereo fully differential output configuration
37		0xC0		power up DACs
12		0x05		DAC De-emphasis
41		0x50		DAC path switch
43		0x00		DAC unmute
44		0x00		DAC unmute
86		0x09		Unmute output
93		0x09		Unmute output






  • Hi, Samuel,

    Welcome to E2E, Thanks for your interest in our products!.

    Could you please provide more details of your application, like input clocks and desired digital format?. I have notified my colleague to take a look to your settings. As he is out of the office, He will take a look and will get back to you in the next couple of days. Thanks for the comprehension.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • Hello Diego,

    I am using a 27MHz clock as the input to MCLK on both chips, I have verified that I am getting the desired output from WCLK (48kHz) as well as BCLK(48kHz*32). I am using I2S for the digital format.

    While I wait for your colleague could you tell me which DAC_L1/2/3 to use to output solely to the LEFT_LOM/P and RIGHT_LOM/P?

    I believe the error is coming from the output/DAC chip as I have probed the DOUT from the master and it appears to be giving correct data, however I could be mistaken.

    Thank you very much for your response,
    Samuel
  • Hi, Samuel,

    DAC_L1/2/3 and DAC_R1/2/3 are not routed to line outputs by default, so you need to configure the desired output  for the DAC source. By default, the DAC output is routed to DAC_x1 (register 41), so  in order to route DAC_L1 to LEFT_LOM/P, register 82 should be configured with 0x80 value. The same applies for register 92 in the case of DAC_R1 to RIGHT_LOM/P. 

    If no mixing is required in the output stage, DAC_L3 and DAC_R3 can be routed directly to X_LOP/M output by configuring register 41 with 0xA0.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • Diego,

    I have tried both and neither have worked. Please let me know what your colleague says about my register settings when he returns.

    I will attempt to look into hardware further in the meantime.

    Thank you.
  • Hi, Samuel,

    First of all, I recommend to use the DAC_L1 / DAC_R1 to LEFT_LOP/RIGHT_LOP path. The output mixers have internal filtering. So, it can be used to reduce output noise. Please configure Page 0 / Register 41 as 0x00 and Page 0 / Registers 82 and 92 as 0x80.

    The PLL could be a root cause too. It seems that the PLL is not enabled. Page 0 / Register 3 is not written in your register settings. Additionally, it seems that the PLL values are wrong. Could you confirm that these are the registers values that you are using? These values give a sampling rate around 40KHz. Please ensure that the PLL is configured to get 48KHz sampling rate.

    P = R = 1
    J = 3
    D = 0321 (register 5 contains the 8 MSB of D; register 6 contains the 6 LSB of D; so D = 0000 0101 0000 01)

    I apologize for this late response. I couldn't answer these days. Thank you for your comprehension.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hello Luis,

    Thanks for the response. I actually just found my issue and it had to do with how I was clocking in DOUT and BCLK/WCLK.

    I do have the settings incorrect for the sample rate and I somehow lucked into getting close to 48kHz but I can do it properly now.

    Thanks for your time and your support,

    Samuel