Part Number: TLV320AIC23B
My customer is asking the following questions regarding the TLV320AIC23B:
The S/W team has had multiple issues with this codec, (channel bounce, MSB bits at different positions, sample packets out of sequence), but when this occurs a s/w reset or hard power cycle solves this until the next boot cycle.
Question: Has TI seen this type of complaint before?
We are spinning the design, and I wanted to solve this problem.
The data sheet for TLV320AIC23 says: DVDD may not exceed BVDD 0.3V; BVDD may not exceed AVDD 0.3V or HPVDD 0.3. Our volume production design meets this requirement, as follows: a. AVDD = HPVDD = 3.0V (this is created from a LDO from the 3,3V supply) b. BVDD = DVDD = 3,3V. Our design meets the data sheet spec.
A separate article SLEA037 says the supply voltage has different requirement to the data sheet, see "4.1 Power Restrictions" Can you tell us what is the correct voltage rules and are there any power up sequencing for the power supply ?
Have we seen issues similar to those reported by the customer? Could the supply voltage restrictions stated in the application note (SLEA037) be the cause of the issues that they are seeing? Is the information contained in this application note valid? It is still listed as a preliminary document. Please let me know if they should follow the application note of the data sheet specifications.
Are there any other problems that could cause the issues that the customer has seen over the years with this IC?
Thanks for your help with this questions!
Richard Elmquist