• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 29 subscribers
  • Views 642 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLV320AIC3256: Input overload

Harald Schilke
Prodigy 30 points
Part Number: TLV320AIC3256

Hello

We use the AIC3256USBEVM to evaluate the AIC3256 mini DSP. In order to do so, we design a simple program with TruePath IDE. There is a framework AIC3256App4x2x, Dec4xIn, DSP_A_DSP_D interprocessor and a Int4xOut output. --> DSP

We want to record at the lineIn1 and to playback the record immediatly at the lineOut (only for test).

Our problem is that a smal input signal greater than 100mV results in saturation of the Output.

According to reference maual: in case of common mode and 0,9V offset it should be possible to input a signal up to 0,5Vss.

A part of our SystemSettingCode:

;-----------------------------------------------------------------------------------

; ADC Channel Configuration

;-----------------------------------------------------------------------------------

reg[ 1][ 51] = 0x40 ; Mic Bias enabled, Source = Avdd, 1.25V

reg[ 1][ 52] = 0x40 ; Route IN1L to LEFT_P with 10K input impedance

reg[ 1][ 54] = 0x40 ; Route CM1L to LEFT_M with 10K input impedance

reg[ 1][ 55] = 0x40 ; Route IN1R to RIGHT_P with 10K input impedance

reg[ 1][ 57] = 0x40 ; Route CM1R to RIGHT_M with 10K input impedance

reg[ 1][ 59] = 0x00 ; Enable MicPGA_L Gain Control, 0dB

reg[ 1][ 60] = 0x00 ; Enable MicPGA_R Gain Control, 0dB

reg[ 0][ 81] = 0xc0 ; Power up LADC/RADC

reg[ 0][ 82] = 0x00 ; Unmute LADC/RADC

　

;-----------------------------------------------------------------------------------

; DAC Channel Configuration

;-----------------------------------------------------------------------------------

reg[ 1][ 12] = 0x08 ; Route LDAC to HPL

reg[ 1][ 13] = 0x08 ; Route RDAC to HPR

reg[ 1][ 14] = 0x08 ; Route LDAC to LOL

reg[ 1][ 15] = 0x08 ; Route LDAC to LOR

reg[ 0][ 63] = 0xd4 ; Power up LDAC/RDAC w/ soft stepping

reg[ 1][125] = 0x12 ; GCHP Mode, Offset corr Enabled on present routing

reg[ 1][ 16] = 0x00 ; Unmute HPL driver, 0dB Gain

reg[ 1][ 17] = 0x00 ; Unmute HPR driver, 0dB Gain

reg[ 1][ 18] = 0x00 ; Unmute LOL driver, 0dB Gain

reg[ 1][ 19] = 0x00 ; Unmute LOR driver, 0dB Gain

reg[ 1][ 9] = 0x3c ; Power up HPL/HPR and LOL/LOR drivers

reg[ 0][ 64] = 0x00 ; Unmute LDAC/RDAC

Thanks for your advice....

  • 0
    TI__Guru* 84915 points
    Hi, Harald,

    Welcome to E2E and thank you for your interest in our products!

    Could you provide the entire process flow file that you are using on PurePath Studio? This would be helpful to have a better approach to this issue.

    Thank you.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 30 points

    Hello Luis Fernando

     

    Thank you for your answer.

    Attached you can find the PurePath files.

    Our goal is our own platform with a Silicon Labs Gecko (M4) controller. In this application we use the MCLK as input clock with 48MHz.

    At the moment we use the PLL to generate the input clock.

    At first we only tried to output a rectangular signal to Lineout. That was successful.

    Then we tried to record from Line-input and transmit this to Lineout. In this case the saturation happened!??!

    This was only to get familiar with the DSP. In our application we need a special filter for two microphones and mono output with 8000Hz data rate plus oversampling.

     

    Another issue is that we don’t understand how to configure the DSP to oversample with 48k or 96k for an output of 8000Hz data stream in mono.

    The first problem is to configure the DSP in the right order to oversample with for example 48kHz and 8000Hz output data.

    The second is the range of the output I2S data. In my understanding the I2S data must be based on 0x8000 +/- 0x7FFF.

    Every time we switch to mono, the result data stream on I2S seems to be based on 0x4000….?

    And all that with an input signal of 50mVss. If we try to input more than 50mV saturation happens.

     

    We are completely confused.

     

    Best regards

    Harald

    3884.test.zip

  • 0 in reply to Harald Schilke
    Prodigy 30 points

    We have solved the problem for our test application.

    First it was a wrong register setup for the clock generation.

    Here our solution:

           %%if (%%prop(SampleRate) == 8000)

           reg[ 0][ 5] = 0xB2       ; P=3, R=2

           reg[ 0][ 6] = 0x02       ; J=2

           reg[ 0][ 7] = 0x02       ; D=0x0230 (MSB)

           reg[ 0][ 8] = 0x30       ; D=0x0230 (LSB)

           reg[ 0][ 4] = 0x03       ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on

           reg[ 0][ 12] = 0x88       ; MDAC = 8, 0x80 = divider powered on

           reg[ 0][ 13] = 0x02       ; DOSR = 640 = 0x280 (MSB)

           reg[ 0][ 14] = 0x80       ; DOSR = 640 = 0x280 (LSB)

           reg[ 0][ 18] = 0x82       ; NADC = 2, divider powered on

           reg[ 0][ 19] = 0xA8       ; MADC = 40, divider powered on

           reg[ 0][ 20] = 0x80       ; AOSR = 128

           reg[ 0][ 11] = 0x82       ; NDAC = 2, divider powered on

           %%endif

    Perhaps it will help other developer…

    It was a realy complex way to calculate this values because of the dependencies between.

     

    The next was a wrong Framework we are using in PurePath.

    Now we use the AIC3256App8x4x_1 framework and the input signal is what we expect.

    Thanks for Help…