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TLV320AIC3254: Loading miniDSP from Linux Driver

Part Number: TLV320AIC3254

Team,

Our customer is modifying the AIC3254 Linux driver to support loading the DSP. They looked at the code that is generated and have the DSP loaded into memory. When the DSP is not loaded the audio works fine but when the DSP is loaded they get noise at 0db levels. In their design, they are using 24.576 clock in the driver and using the driver to set audio rate and interface setup. They have looked at the registers and everything is loaded as expected, and they have tested the simple treble shelf app on the dev kit. They are wondering if there is something going on with the actual MCLK rate given it is different from the clock on the dev kit. Everything is being run at 48kHz.

Any ideas on what could be going wrong? They are writing all registers that are related to DSP but routing and other setup is handled by the driver.

Thanks,

Antonio

  • Including some additional customer details below. Please let me know if you need any other info or register captures:

    I think this is a larger issue with what is generated from the PurePath Studio.  On output I just have a straight shot out and I am getting a very bad sine wave output.  This is a 2k sine wave that is normally very clean. When not running through the DSP.  This is the absolute simplest of apps for the dsp but I see no area in the studio to edit for device clock rate, bit width and the like.  

  • Hi, Antonio,

    If the miniDSP code is working as expected using the EVM, I think that as you suggest he clock differences between EVM and end-system could be causing the issue.

    Can you please verify that the process flow on the PurePath Studio is configured for 48KHz operation?. Another thing to consider is that if in the end-system the master clock is 24.576MHz, in the EVM is 11.2896MHz so proper adjustments should be done in the end-system clock generation. One thing to try would be to hook the clock frequencies used in the end-system to the EVM and check if the noise can be repeated. Also, loading the settings from the Linux Driver to the EVM could be a good test to perform.

    The clocks are not configured in PurePath Studio and the only parameter chat can be changed is the sampling frequency used. Having the frequencies of the clocks used by customer  and register settings for the clock configuration would be really helpful to check what could be the root cause of the issue.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • Diego,

    I am the customer having the issue.  I just tested the data interface and it is 48kHz signed 16bit little endian data and i can force this format using ALSA configuration.  I dont really think that i could get the linux driver to setup the dev kit without a good bit of work as we are using the little USB one not the full kit and its processor has a 6MHz clock so i dont know what the MCLK would be.   I am going to include the register dump and the code generated by PurePath.  From what i can see the code is being perfectly placed into DSP memory.

    0753.regdump.txt
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    dsp.h

  • Hi, Ed,

    Thanks for the feedback. I was looking at the Process Flow image sent by Antonio and noticed that the incorrect interpolator block is selected. In your flow, Int2xOut is used, this block is compatible with quad-rate sampling frequencies, like 192KHz. For a 48KHz sampling rate, the Int8xOut should be selected. Can you please try changing the Interpolator block used?. 

    That being said, I performed some tests with the TLV320AIC3254EVM-K and was able to kind-of replicate the issue, I used the Int2xOut interpolator and provided external 48KHz sampling rate clocks. PPS process flow was setup to operate at 48KHz as well. The issue was replicated by changing the clocks provided to the EVM after the initial device configuration, so this makes me think that the clock setup is the problem in your system. Can you please share the whole clock setup used in your end-system?.

    Thanks and Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • Diego,

    I updated to use 8x output and it only added a few more steps the output still looks like a pyramid.  The configuration of the Clock is done through the ALSA constructs but i can do my best to give you parameters.  In my configuration i have the TLV320 acting as the clock master for FCLK and BCLK and they are correct at 48kHz and 1.536MHz and this is with 16bit data.  I checked the code output and it does not adjust the data field after reset so one must assume 16bit data.  Below is the code for hardware setup in the driver and the paramters for 48kHz are included.  Let me know if anything else is needed.  It is to be noted that these parameters are fine when working without DSP as we have been using this product for over a year and are just now in Beta and wanting to add some DSP to get proper frequency response.

    MCLK = 24576000
    rate = 48000
    p_val = 2
    pll_j = 8
    pll_d = 0000
    dosr = 128
    ndac = 8
    mdac = 2
    aosr =64
    nadc = 8
    madc = 4
    bclk_N = 4

    /* Use PLL as CODEC_CLKIN and DAC_MOD_CLK as BDIV_CLKIN */
    	snd_soc_write(codec, AIC32X4_CLKMUX, AIC32X4_PLLCLKIN);
    	snd_soc_write(codec, AIC32X4_IFACE3, AIC32X4_DACMOD2BCLK);
    
    	/* We will fix R value to 1 and will make P & J=K.D as varialble */
    	data = snd_soc_read(codec, AIC32X4_PLLPR);
    	data &= ~(7 << 4);
    	snd_soc_write(codec, AIC32X4_PLLPR,
    		      (data | (aic32x4_divs[i].p_val << 4) | 0x01));
    
    	snd_soc_write(codec, AIC32X4_PLLJ, aic32x4_divs[i].pll_j);
    
    	snd_soc_write(codec, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8));
    	snd_soc_write(codec, AIC32X4_PLLDLSB,
    		      (aic32x4_divs[i].pll_d & 0xff));
    
    	/* NDAC divider value */
    	data = snd_soc_read(codec, AIC32X4_NDAC);
    	data &= ~(0x7f);
    	snd_soc_write(codec, AIC32X4_NDAC, data | aic32x4_divs[i].ndac);
    
    	/* MDAC divider value */
    	data = snd_soc_read(codec, AIC32X4_MDAC);
    	data &= ~(0x7f);
    	snd_soc_write(codec, AIC32X4_MDAC, data | aic32x4_divs[i].mdac);
    
    	/* DOSR MSB & LSB values */
    	snd_soc_write(codec, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
    	snd_soc_write(codec, AIC32X4_DOSRLSB,
    		      (aic32x4_divs[i].dosr & 0xff));
    
    	/* NADC divider value */
    	data = snd_soc_read(codec, AIC32X4_NADC);
    	data &= ~(0x7f);
    	snd_soc_write(codec, AIC32X4_NADC, data | aic32x4_divs[i].nadc);
    
    	/* MADC divider value */
    	data = snd_soc_read(codec, AIC32X4_MADC);
    	data &= ~(0x7f);
    	snd_soc_write(codec, AIC32X4_MADC, data | aic32x4_divs[i].madc);
    
    	/* AOSR value */
    	snd_soc_write(codec, AIC32X4_AOSR, aic32x4_divs[i].aosr);
    
    	/* BCLK N divider */
    	data = snd_soc_read(codec, AIC32X4_BCLKN);
    	data &= ~(0x7f);
    	snd_soc_write(codec, AIC32X4_BCLKN, data | aic32x4_divs[i].blck_N);