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TLV320AIC3106: white noise

Part Number: TLV320AIC3106
Other Parts Discussed in Thread: AM3352

we are driving the codec via the McASP on an AM3352. we don't seem to have a problem communicating with the codec via I2C or the data lines

we are in DSP mode, 16 bit, 8KHz FS. codec is master for FS and WCLK. Input is a 24.576MHz oscillator. we are on a custom board, not an EVM

we have an issue with white noise on the DAC lines. it appears to be white noise. when audio is played out the DAC we can hear the audio but the white noise is always there. we are sending all 0x0000's to the codec for TX samples so it isn't the signal we are trying to play (it's hard to mess up 0's). if i mute the codec it goes away, if i apply gain to the DAC is appears. the amount of gain i apply to the DAC has no effect on the amplitude of the noise. 

i should mention this is the first couple of days of using this codec so i am not an expert by any means.

we are using (for input) Line1L, Line1R, Line2R, Line2L and (for output) MONO_LO, HPROUT/COM, RIGHT_LO, LEFT_LO

here are the settings and the order in which we set them:

Reg 15 <- 0x80 (mute)

Reg 16 <- 0x80 (mute)

Reg 43 <- 0x80 (mute)

Reg 44 <- 0x80 (mute)

Reg 2 <- 0xAA (FS/6)

Reg 5 <- 0 

Reg 6 <- 0 (D=0)

Reg 4 <- 0x10 (J=16)

Reg 11 <- 1 (R = 1)

Reg 3 <- 1 (P = 1)

Reg 25 <- 0x40 (2V micbias)

Reg 19 <-  0xFF (Line1L diff, Left ADC powered up, Left ADC no soft step, Line1L not connected Left ADC)

Reg 22 <- 0xFF (line1r diff, right adc powered up, right ADC no soft setp, Line1R not connected right ADC)

Reg 23 <- 0x80 (line2R differential)

Reg 78 <- 0x80 (DACR1 to MONO_LO)

Reg 89 <- 0x80 (DACL1 to RIGHT_LO)

Reg 61 <- 0x80 (DACL1 to HPROUT)

Reg 37 <- 0xC0 (right and left DAC powered up)

Reg 79 <- 0x09 (MONO_LO powered up, unmuted)

Reg 7 <- 0x0A (enable right and left data path)

Reg 9 <- 0x40 (DSP mode)

Reg 8 <- 0xD0 (BCLK and WCLK output, enable clocks to run)

one input is always on so that gets set

Reg 16 <- 0 (right ADC +0dB)

the system will then select a particular output when an action is done on the board:

we right set the gains for one input

Reg 16 <- 15 (right ADC +7.5dB)

then we set the gain for another set

Reg 43 <- 0x80 (mute left DAC)

Reg 20 <- 0xFC (unroute Line2L from left ADC, Line2L differential, Left ADC biased to common mode voltage - unroute for a CYA, is this needed?)

Reg 21 <- 0x78 (unroute Line1R off left ADC - unroute for a CYA, is this needed?)

Reg 41 <- 0x40 (Left DAC to Left Line Out DAC_L3)

Reg 19 <- 0x87 (Line1L differential, Left ADC powered up, Left ADC no soft step)

Reg 65 <- 0 (power down HPROUT)

Reg 93 <- 0 (power down RIGHTLO)

Reg 86 <- 0x09 (LEFT_LO unmute, powered up)

Reg 15 <- 0x0F (set ADC=7.5dB)

Reg 43 <- 60 (Left DAC attentuation -30dB)

and white noise. since i am so new to this codec i don't know if i am missing a setting. i didn't turn on any filtering or AGC, and i didn't see any settings after looking over all the registers that jump out at me for noise. i'm not asking you to fix my board if it is board noise, but if i am missing an important setting or setting up the codec wrong i would sure like to know. thanks.

  • Hello Cobsonchael,

    I'm sorry you're experiencing some difficulties. I'm sure we can help you get this under control.

    First lets start with your PLL. You set Fref in register 7 to 48khz. But your PLL settings don't match.

    For the PLL we have the following equation found in section 11.3.3.1 of the datasheet.
    Fsref = (PLLCLK_IN x K x R)/(2048 x P), Where K= J.D
    your settings give us

    (24.58MHz * 16 *1)/ (2048*1) = 192kHz

    You also need to follow the constraints for the PLL when D = 0000
    2 MHz ≤ ( PLLCLK_IN / P ) ≤ 20 MHz => You do not meet this criteria with your settings
    80 MHz ≤ (PLLCLK _IN × K × R / P ) ≤ 110 MHz => you do not meet this criteria with your settings
    4 ≤ J ≤ 55

    If you change P to 2 and J to 8 you can get the correct Fsref = 48khz and meet the PLL constraints.

    Would you mind checking to see if that solves your issue?

    best regards,
    -Steve Wilson
  • my apologies it has been a while since i did this part of my custom board. J = 4 which gives me 48KHz. i forgot to shift the value by 2

    i will try your settings and see if that solves my issue
  • I wondered if there might have been something like that going on... I was trying to figure out how the device would be working at all with an Fsref of 192k.

    regardless, even with J = 4 the PLL is still not meeting all of the recommended criteria.

    change P to 2 and J to 8 and lets see how that goes.

    best regards,
    -Steve
  • i made the changes and unfortunately it did not affect my white noise issue
  • I suppose that would've been too easy. Oh well, I'll take a look at the register settings again and get back to you yet this afternoon.

    best regards,
    -Steve Wilson
  • to make this your register writes easier to read, I'm removing redundant lines (where the value written to the register is equal to the default value) I changed the ordering, just for the sake of making it easy to read.

    start with a software reset, this will ensure that the device is always from a known state at startup.

    reg 01 <-0x80 (software reset)
    Reg 2 <- 0xAA (FS/6)
    Reg 3 <- 0x02 (P = 1)
    Reg 4 <- 0x20 (J=8)
    Reg 5 <- 0x00
    Reg 6 <- 0x00 (D=0)
    Reg 7 <- 0x0A (Fsref = 48kHz, enable right and left data path)
    Reg 8 <- 0xD0 (BCLK and WCLK output, enable clocks to run)
    Reg 9 <- 0x40 (16-bit DSP mode)
    Reg 11 <- 1 (R = 1)
    Reg 16 <- 0x00 (right ADC unmuted, PGA gain = +0dB)
    Reg 19 <- 0x87 (Line1L differential, Left ADC powered up, Left ADC no soft step)
    Reg 20 <- 0xFC (unroute Line2L from left ADC, Line2L differential, Left ADC biased to common mode voltage - unroute for a CYA, is this needed?)
    Reg 22 <- 0x7F (line1r diff, right adc powered up, right ADC no soft setp, Line1R not connected right ADC)
    Reg 23 <- 0x80 (line2R differential, input level control gain = -12dB)
    Reg 25 <- 0x40 (2V micbias)
    Reg 37 <- 0xC0 (right and left DAC powered up)
    Reg 41 <- 0x40 (Left DAC to Left Line Out DAC_L3)
    Reg 43 <- 60 (Left DAC attentuation -30dB)
    Reg 65 <- 0 (power down HPROUT)
    Reg 61 <- 0x80 (DACL1 to HPROUT)
    Reg 78 <- 0x80 (DACR1 to MONO_LO)
    Reg 79 <- 0x09 (MONO_LO powered up, unmuted)
    Reg 86 <- 0x09 (LEFT_LO unmute, powered up)
    Reg 89 <- 0x80 (DACL1 to RIGHT_LO)
    Reg 93 <- 0 (power down RIGHTLO)

    So it seems like you are hooking DAC_L1 or DAC_R1 to all of your outputs, but you hook up the LeftDAC to DAC_L3 (register 41) although the right dac is set to the DAC_R1 path.

    Can you change the register 41 setting to 0x00?
    Do all of the outputs have the same noise?

    Can you run the above set of register writes, starting with a software reset. and see where we stand?

    best regards,
    -Steve Wilson
  • so no change when registers are ordered as you have them laid out.

    so our system work like this: the right DAC and ADC are paired to an input and output that does not change. the left DAC has to switch between 3 different outputs and 2 different inputs. i route DAC_L1 to 2 different outputs so when we switch to those outputs i don't have to add more register writes to the process. i use DAC_L3 because the output i am focusing on right now is LEFT_LO which is tied directly to DAC_L3 and in the datasheet it states that if we are using that output and don't require an mixing (we don't) then it is best to use DAC_L3

    i have tried another output path for the left DAC and used DAC_L1 to output from the RIGHT_LO and it also has considerable white noise. i have not checked out the right DAC at all
  • i should take that first statement back

    i am flip flopping around between sending silence and sending known audio frequencies. when i send silence now i do actually get silence. when i send a sine wave i get a boat load of white noise
  • so even when i write just a constant to the transmit interrupt i get noise (writing 1000 for example) but still when i write 0's, no noise.

  • Hi Cobsonchael, I haven't forgotten about you. Thanksgiving week gets oddly busy, but I'm working on replicating your setup in the lab. can you disable the PLL and just use the clock divider instead? just to see if somehow the PLL is involved?

    w 30 03 20
    w 30 65 01

    -Steve Wilson
  • i disabled the PLL and used Q=4 as my divider, leaving Fs/6 in place. it did not solve my issue

    the holidays are always a hectic time to solve these issues. hopefully you can still find some time to enjoy them

    what are the 'w' numbers?
  • ah, sorry. when using our GUI that the format we use. for register reads and writes
    w = write
    30 is the address of the device (the actual address is 7 bits: 0011000 ) but when another pad 0 is added for 8 bit communication, it becomes 00110000 or 0x30

    -Steve
  • so why write to register 65?

    so this is weird. you gave me values for the registers with the PLL disabled (reg3 = 0x02) and i tried with both the pll really enabled and pll really disabled with the right values and still noise.

    here are some picture of the noise on my output (differential lines) in case it helps

  • Register 0x65 = register 101.  its all in hex.

    That is a lot of noise on the scope shots.  Can you send me a recording of the noise?  l wonder if this is an audio format problem.  

    I've got your register settings connected to an EVM in the lab, I can listen to headphones,  and it is super quiet.  I will say that I hadn't connected the AP to an AIC310x device in DSP mode for a long time, so it took a few minutes to really get the settings on the AP right,  but its dead quiet now.

    I'll attach some screen shots I took.  The first one, is from the HPLOUT.   The settings on my scope mirror yours.

    The second shot is test point FLP on our EVM which puts a LPF on the output of the HPLOUT to filter out of band noise.   I had to change the settings on the scope for that one,  it's clearly much better.  

    That being said,  the headphone out on the EVM does not use the filter, and using headphones there really isn't any noticeable white noise.

    When I was setting up the AP, if I didn't have the settings right, I definitely got a lot of what could be called "white noise".  What may be 'happening is your DSP and your Codec aren't quite in sync.  Refer to section 10.3.2.4 in the Datasheet for what the Codec is expecting.  Send me a recording too.  That will give me a better idea of what you are seeing/hearing

    best regards, 

    -Steve 

  • ALso, If it is not an audio format disconnect,  you may take a look at the application report entitled "Common Noise Issues in Audio Codecs".

  • this is a new board that just got this far for the codec, so i am not ruling out any board issues.

    i'll have to work on getting you some kind of recording

    i would be willing to bet it could be an issue with the McASP communicating with the codec. we have never done McASP before either (this codec is new to us). however, when i halt my emulator and kill all communication with the codec the noise is still there. i tried switching to I2S and that didn't make any difference either. the noise seems to be unaffected by the DAC gain, i send a sine wave out, and raise the volume and the sine wave gets louder but the noise does not.
  • I’ve reached out to the sitara team, but can you tell me more about how the McASP is configured?
    Best regards,
    -Steve
  • If the noise is there regardless of whether there is any communications with the codec or not, It may be layout related. Can you send me the PCB file? I can put another set of eyes on it to see if I can see anything that might be problematic.

    So the Digital gain doesn't seem to affect anything. what about if you change the mixer(analog) gain? you mentioned before that if you mute or shutdown the DAC that the noise goes away right?

    -Steve
  • i'll have victor send the PCB file

    when i change the gain in register 86 between 0 and 9dB the noise gets way worse as the gain goes up. yes, if i mute the DAC the noise goes away

    mcASp is configured with the codec as I2S right at this moment. 1 bit delay, polarity 1 for bit clock (sample on rising edge, output on falling), polarity 1 for FS (falling edge initiates frame), 16 bit, 2 slots/frame. do you want register values?
  • Michael, I got the board files. Thanks for sending them. I'll take a look and get back to you. 

    can you remove the 1 bit delay? make it 0 bit.  The Codec is also set up for I2S then?  

    I would definitely take the register values.  just the ones you set is fine. 

    best regards, 

    -Steve

  • yes i changed the codec setting for register 9 to be 0 = I2S 16 bit mode

    here are what i think are the important TX register settings:

    MCASP0_XMASK -> 0xFFFF0000

    MCASP0_XFMT -> (1<<16) | (7<<4) | (1<<3) | (1<<15)

    MCASP0_AFSXCTL -> (2<<7) | (1<<4) | 1

    MCASP0_ACLKXCTL -> (1<<7)

    MCASP0_AHCLKXCTL -> 0

    MCASP0_XTDM -> 3

    MCASP0_XINTCTL -> (1<<5) | (1<<1) | 1
  • Michael,

    I'm unfamiliar with your notation, would you mind explaining it?

    -Steve
  • i assume you are familiar with the mcasp registers

    the values assigned are more like code, so i don't make a mistake when making hex values in my head.

    register -> (1<<2) is the same as register -> 0x04. i shift it over by the number of bits the data field exists that i am trying to write to
  • Ahh, that makes total sense. I tend to live in hex on the codec side.
    I'll check out the settings now and get back to you
  • i shared the noise document with our board layout guy and here is his response:

    "One thing they mention is separating the analog and digital grounds. We have never done that, but it could make a difference. They also say the decoupling caps should be on the same side of the board as the CODEC itself. Ours are on the opposite side."
  • Michael,

    I'm going to take a look at your PCB with the processor team tomorrow and we'll hopefully we'll be able to see the issue.

    separating analog and digital ground will definitely help, but I wouldn't expect that to cause the kind of noise levels that you are seeing.
    I mean, the scope shots you posted showed 1.25V difference between peaks. I just feel like that is way too much noise for decoupling/ground issues.
    One thing we could do is use the PGA bypass feature for the Ext mic input and pass that through to one of the Analog outputs.
    for example, for HPROUT you can use Register 53 or 56 depending on if you want to use the Right or left input PGA.
    then lower the DAC_L1 volume using Register 54. If you can hear the input clearly, and there is no noise, then I am more convinced than ever that we have an audio formatting issue.

    I'll test this tomorrow with Mark but if you have time today, give it a shot.

    -Steve
  • here is what i did:

    did not init the McASP at all. no McASP samples at all. i routed from a known input signal (telephone line) to a speaker. the noise was still there and the telephone signal sounded normal on top of it. i'm leaning toward some kind of board noise. when i take samples out of the phone line and graph them inside code composer they look very clean so it's only on the tx side. what do you think?
  • The only thing that confuses me is that you said if you mute the DAC,  the noise goes away.  So if you Mute the DAC now,  is the signal from the phone clear without noise?

    Best regards, 

    -steve

  • in this mode, when i mute the DAC and even comment out it being powered up the noise it still there so i don't know if i got something wrong when i tested it before or this is a new scenario.
  • Interesting.
    As I mentioned, I'm meeting up with the sitara team today and we're going to test the pcbs you sent them. We should be able to reproduce this problem, and then try to find out where the noise is coming from.

    best regards,
    -Steve
  • sounds good. i did update my project that i uploaded to the box so it recreates the noise issue. "cutdown 3352.zip"
  • Michael,

    we had some problems getting the project to build but we were able to use the out file to at least hear the white noise. Mark was able to resolve the build problems and we'll give it another shot this afternoon.

    I will keep you posted.

    best regards,
    -STeve