• Resolved

TLV320DAC3203: The frequency response is -6dB in 32k sample rate I2S interface with interpolation filter C: PRB_P17. The group delay is 11/Fs, not 13/Fs?

Part Number: TLV320DAC3203


I test the following code in audio precision (Digital serial: out ; analog: in)

What I got the frequency response is -6dB and group delay is less than datasheet suggest.(Datasheet said group delay(Typical?) =13/Fs in filter C case.

The group delay in my measurement is 0.33ms~11/Fs?!.)

To make sure, is there any possible wrong in my code? (Measurement setting in AP seems alright because when testing other codec it is fine.)

Ps. I use 4M crystal input to MCLK pin. Codec output BCLK and WCLK clock into Audio Precision digital serial port. The whole code is for 32k sample rate application.

{0x00, 0x00}, // 0. Initialize to page 0
{0x01, 0x01}, // 1. Initialize the device through software reset
{0x04, 0x03}, // 2. Set PLL_CLKIN as MCLK and CODEC_CLKIN as PLL_CLK
{0x05, 0x93}, // 3. Power up PLL, set PLL divider P=1 and PLL divider R=3
{0x06, 0x07}, // 4. Set PLL divider J=7
{0x07, 0x00}, // 5. Set PLL divider D=0000
{0x08, 0x00}, // 6.
{0x0b, 0x83}, // 7. Power up and set NDAC divider = 3
{0x0c, 0x87}, // 8. Power up and set MDAC divider = 7
{0x0d, 0x00}, // 9. Set DOSR = 128 MSB //for32Khz
{0x0e, 0x80}, //10. Set DOSR = 128 LSB //for32Khz
{0x1b, 0x3c}, //11. Set I2S interface, Word length 32 bit, BCLK output, WCLK output
{0x3c, 0x11}, //12. DAC mode to PRB_P17
{0x1d, 0x05}, //13. BDIV_CLKIN = DAC_MOD_CLK
{0x1e, 0x82}, //14. Power up and set BCLK N divider = 2 //for 32KHz
{0x00, 0x01}, //15. Select page 1
{0x01, 0x08}, //16. Disable internal crude AVdd in presence of external AVdd supply
{0x02, 0x00}, //17. Enable master analog power control
{0x7b, 0x01}, //18. Set the REF charging time to 40ms
{0x0a, 0x00}, //19. Set the input common mode to 0.9V and output common mode for headphone to input common mode
{0x0c, 0x08}, //20. Route left DAC & INL to HPL
{0x0d, 0x08}, //21. Route right DAC & INR to HPR
{0x03, 0x00}, //22. Set the DAC PTM mode to PTM_P3
{0x04, 0x00}, //23.
{0x10, 0x00}, //24. Set the HPL gain to 0dB
{0x11, 0x00}, //25. Set the HPR gain to 0dB
{0x14, 0x29}, //26. HP soft stepping settings for optimal pop performance at power up. Rpop used is 6k with N = 6 & soft step = 20usec
{0x09, 0x30}, //27. Power up HPL and HPR drivers
//#----------- Wait for 2.5 sec for soft stepping to take effect
//#----------- else read page 1, register 63d, D(7:6). When = “11” soft-stepping is complete
{0x00, 0x00}, //28. Select page 0
{0x44, 0x00}, //29. DRC Control Register 1 , disable DRC
{0x3f, 0xd6}, //30. Power up the left and right DAC channels and route the left channel I2S data
// to left channel DAC and right channel I2S data to right channel DAC
{0x40, 0x00} //31. Unmute the DAC digital volume control


Y.W. Fan