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CCS/TLV320AIC3106: 96kHz sampling rate on TMS320C6748 LCDK

Part Number: TLV320AIC3106
Other Parts Discussed in Thread: TMS320C6748

Tool/software: Code Composer Studio

Good Afternoon,

I have a TMS320C6748 LCDK that I am attempting to achieve a 96kHz sampling rate on this unit.  However, I have not been able to do such.  I have been able to achieve a 48kHz sampling rate however, when trying to get a 96kHz sampling rate I get nothing but I get silence from the codec when generating a sine wave.

Q=4
PLL Disabled

Dual Rate Mode Enabled
Register 2: 00000000
Register 7: 01101010
Register 3: 00100010

WCLK: 96kHz
MCLK: 24.576kHz
BCLK: 3.049MHz

I've also tried

Q=2
PLL Disabled

Dual Rate Mode Enabled
Register 2: 00000000
Register 7: 00001010
Register 3: 00010010

WCLK: 96kHz
MCLK: 24.576kHz
BCLK: 3.049MHz

In both of these cases I have CLKDIV_IN to be set to MCLK which is 24.576MHz

Either of these seem like the correct setup according to some of the help provided here on the forum already but I haven't had luck with either of these.

  • Hello Tyler,

    Are you able to get the AIC3106 working at 48khz? Your settings look correct, but I"d like to make sure you're routing the DIN to the outputs you want. Can you provide your full configuration?

    best regards,
    -Steve Wilson
  • Steve,

    I am able to get it working at 48kHz no problem. Is there an easy way to type out the configuration or should I manually type it out?

    Is there any specific register configuration you are looking to monitor? Should both of these settings work?

    Tyler
  • Hi Tyler,

    I am testing this in the lab right now. I set up the AIC3106 as the master, just so I could make sure that the ASI was getting the clocks right. I am able to get audio out of the headphones with this script.
    This is simply a modified preset config from the GUI, where I modify Reg 02, 03, 07,08, to match your config.
    The Codec spits out the 96khz wclk, and the I2S data sent from the AP is coming out as audio on the HPL/ROUTs.
    here is the configuration

    w 30 01 80
    w 30 03 22
    w 30 07 6a
    w 30 08 c0
    w 30 11 0F
    w 30 12 F0
    w 30 16 7C
    w 30 13 7C
    w 30 0F 00
    w 30 10 00
    w 30 19 80

    w 30 11 0F
    w 30 12 F0

    w 30 29 02
    w 30 2B 00
    w 30 0E C0
    w 30 25 E0
    w 30 26 10
    w 30 2F 80
    w 30 40 80
    w 30 41 0D
    w 30 33 0D

    I also tested this in Slave mode (changed R08 to 0x00) and then set the BCLK and WCLK to outputs on the AP. It also works for me.

    can you give me more info on your application? what are you using to send the I2S Data?
  • The Application is with a TMS320C6748LCDK.  I went to troubleshoot the code further but it appears as though my evm is having trouble with interrupts.  At first, it wouldn't enter the interrupt all the time and now it won't enter the interrupt at all. (Interrupt 4 of TMS320C6748LCDK)  This trend only seems to be occurring with interrupt routines so I will have to investigate further into the interrupt routines I guess.

    Thank you confirming that my register setup is correct, if anyone has any input on interrupts, it would be greatly appreciated.

    Tyler

  • Tyler,

    I'm not really familiar with the TMS320C6748, But if you post in the DSP forum, I"m sure someone would be able to help you.

    best regards,
    -Steve Wilson