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Original question:

TLV320AIC3104: I2C

TLV320AIC3104: I2C

Santhoshkumar Mallula
Prodigy 80 points
Part Number: TLV320AIC3104

Hello All,

We are testing TLV320AIC3104 IC using Automatic test equipment (Advantest V93K). By making AIC3104 as slave, we could write all the registers and read back the same except Regiter-86 and Register-93. These two registers are responsible for LEFT/RIGHT_LOP/M Output Level Control Registers.

In these registers, the D1(read only) bit is expected to be '0' - which means " all programmed gains are applied". But we are reading '1' . Since it's a read only bit, is any other register need to be programmed additionally.

iovdd 3.3 V
dvdd 1.8 V
avdd 3.3 V
drvdd 3.3 V

Tried with both 10K and 1K pull up on SCL, SDA. 

Please help us. Are we missing something in programming.

  • 0
    TI__Mastermind 30030 points
    Santhoshkumar,

    Its funny you should bring this up, I was just looking at this. I'm going through the AIC310x family datasheets correcting errors, and this was on my list.

    I've asked the design team to comment for certain, but it appears that this is an error.

    I believe it should read:

    D1 = 0 when "not all programmed gains to RIGHT_LOP/M have been applied yet".
    D1 = 1 when "all programmed gains to RIGHT_LOP/M have been applied".

    Note that the reset value is incorrect too it should be '0'.


    I will confirm with you once I hear back from the design team.

    best regards,
    -Steve Wilson
  • 0 in reply to Steve-Wilson
    Prodigy 80 points

    Hi Steve Wilson,

    Thank you for the reply :) . we are stuck at this point. Your confirmation allow us to proceed further.

    Regards,

    Santhoshkumar M

  • 0 in reply to Santhoshkumar Mallula
    TI__Mastermind 30030 points

    Santhoshkumar,

    I have tested the behavior of the D1 and there are a few things I can say with certainty.

    1.  The reset value of D1 is definitely 0.

    2. D1 does not become 1 until Left_LOP/M is powered up.  

    I've also found another E2E thread about this for a similar device from a few years back, which agrees with my previous analysis. 

    I think the only thing I am uncertain on is if there is any interaction between the volume settings of the mixer that feeds the outputs and the state of D1.  

    Best Regards,

    -Steve Wilson