TLV320AIC3101: TLV320AIC3101 initial setting

Hi All,

Is TLV320AIC3101 the same as TLV320ADC3101??
We decide to use TLV320ADC3101 for our solution.
Please help us!

Thank you very much

Best Regards
nady

hello Eddie,

We would need to know a bit about the application. I can send you any number of initial settings, that enabled different inputs and outputs that was written with a specific MCLK frequency and audio sampling rate,  but it might not be helpful.   here is a folder full of example configurations, but I believe they all assume 44.1khz sampling rate and 11.289 MLCK.

if you let me know their clk frequencies I can always modify these. just let me know.

best regards, 

-Steve Wilson

Example_Scripts.zip

Hello Eddie,

I haven't heard back from you, are you still needing some help with this? please let me know, I'm happy to help
best regards,
-Steve wilson

Hi Steven,

Thanks, Customer would like know register setting with below configuration,

1. Interface : I2S

2. Sample rate : 8KHz

3. Frame rate 16bits

4. TDM mode connect x2 TLV320ADC3101 (total 4 audio channel)

Thanks & regards

Eddie

Hi Steven,

Could you provide me how to make TLV320ADC3101 be a master( output BCLK 512KHz or higher) in 25MHz MCLK

Sorry, I have tired all day, but I don't have any BCLK

These are my register setting for codec:

Page 0 / Register 0(0x0) = 0x0
Page 0 / Register 1(0x1) = 0x0
Page 0 / Register 2(0x2) = 0x20
Page 0 / Register 3(0x3) = 0x0
Page 0 / Register 4(0x4) = 0x0
Page 0 / Register 5(0x5) = 0xa1
Page 0 / Register 6(0x6) = 0x7
Page 0 / Register 7(0x7) = 0x21
Page 0 / Register 8(0x8) = 0xc3
Page 0 / Register 9(0x9) = 0x0
Page 0 / Register 10(0xa) = 0x0
Page 0 / Register 11(0xb) = 0x0
Page 0 / Register 12(0xc) = 0x0
Page 0 / Register 13(0xd) = 0x0
Page 0 / Register 14(0xe) = 0x0
Page 0 / Register 15(0xf) = 0x0
Page 0 / Register 16(0x10) = 0x0
Page 0 / Register 17(0x11) = 0x0
Page 0 / Register 18(0x12) = 0xb0
Page 0 / Register 19(0x13) = 0x82
Page 0 / Register 20(0x14) = 0x80
Page 0 / Register 21(0x15) = 0x80
Page 0 / Register 22(0x16) = 0x4
Page 0 / Register 23(0x17) = 0x0
Page 0 / Register 24(0x18) = 0x0
Page 0 / Register 25(0x19) = 0x0
Page 0 / Register 26(0x1a) = 0x1
Page 0 / Register 27(0x1b) = 0xd
Page 0 / Register 28(0x1c) = 0x0
Page 0 / Register 29(0x1d) = 0x6
Page 0 / Register 30(0x1e) = 0x81
Page 0 / Register 31(0x1f) = 0x0
Page 0 / Register 32(0x20) = 0x0
Page 0 / Register 33(0x21) = 0x10
Page 0 / Register 34(0x22) = 0x0
Page 0 / Register 35(0x23) = 0x0
Page 0 / Register 36(0x24) = 0x0
Page 0 / Register 37(0x25) = 0x0
Page 0 / Register 38(0x26) = 0x3
Page 0 / Register 39(0x27) = 0x0
Page 0 / Register 40(0x28) = 0x0

Thank you very much 

Best Regards

nady

Sorry, It is wrong that we don't need to use codec in master
Please ignore this request

Hi Eddie,

What is your MCLK? master or slave? which inputs, which outputs?

best regards,
-STeve Wilson

Nady,

are you and Eddie working on the same project?

I looked at your configuration and there are definitely some issues, just let me know if you still need assistance.

best regards,
-Steve Wilson