• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Answers 1 answer
  • Subscribers 29 subscribers
  • Views 1149 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLV320AIC3204: Supported MCLK range for AIC3204 codec

Pratik Mevada
Prodigy 60 points
Part Number: TLV320AIC3204

Hi All,

We are going to use TLV320AIC3204 codec in our board. We have query related to MCLK range supported by 3204 codec. As a part of POC I have used 11.2896 MHz frequency provided by USB-MODEVM and I am able to capture/playback audio from my qualcom snapdragon based board. 

I have also tried to externally provide 24MHz frequency but I am not able to capture/playback audio with this clock.

It would be good if someone can let me know different MCLK range supported and I2C configuration required for capture/playback working.

Thanks in advance.

-Pratik  

  • 0
    TI__Guru 57800 points

    Hi, Pratik,

    There are a couple consideration points about this question. The AIC3204 is a codec with flexible clock configurations, it can accept a MCLK of 24MHz but the internal clock tree must be configured for it.

    The EVM of the AIC3204 is compatible with the 11.2896MHz MCLK provided from the motherboard, and as it is the default configuration, the scripts from the GUI configures the internal clock tree to operate with that clock. The clock configuration of the device also requires to take into account the sampling rate of the system and processing blocks selected. I can help with the clock configurations for your application, can you share the sampling rate of your system and processing block selected?. 

    A configuration script example for the clock configuration of the device with a 44.1KHz sampling rate and 24MHz MCLK used as input for the clock tree would be as follows:

    ###########################################################
    # Clock configuration of AIC3204
    # MCLK = 12MHz
    # Sampling Rate = 44.1KHz
    ###########################################################

    w 30 04 03 # CODEC_CLKIN = PLL_CLK, PLL_CLKIN = MCLK
    w 30 05 A1 # P = 2, R = 1, PLL ON
    w 30 06 07 # J = 7
    w 30 07 02 # D = 560
    w 30 08 30 # D = 560
    w 30 12 85 # NADC = 5
    w 30 13 83 # MADC = 3
    w 30 14 80 # AOSR = 128
    w 30 0B 85 # NDAC = 5
    w 30 0C 83 # MDAC = 3
    w 30 0D 80 # DOSR = 128

    As you can see, the PLL is used to generate the internal clocks as 24MHz is not a standard audio frequency.

    Please also take into account that when using the EVM, if you want to provide external clocks from a different processor, the dip switch SW2 of the motherboard should be set so the switches 4 and 5 are on OFF position.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Prodigy 60 points
    Hi,

    Thanks for replay

    I have tried as per your suggestions with my board. I have also tried clock configuration with EVM board with external 24MHz MCLK but I am not able to capture or playback with 24MHz MCLK.
    It will be great if you give some more point to this.

    Thanks
    Pratik
  • 0 in reply to Pratik Mevada
    TI__Guru 57800 points

    Hi, Pratik,

    Thanks for the feedback. The only required change for the device to work with 24MHz MCLK is done with the clock settings. It would help if you can share the register settings you are using with the EVM so I can try replicating it on my side and see if there is something missing for the 24MHz MCLK operation. Apart from the MCLK change, is there something else different between the system which works?. 

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Prodigy 60 points

    Hi,


    I have attached register settings of page 0 and page 1.

    Please review it and give your feedback


    Thanks

    Pratik2318.TI_PAGE_0_REGISTERS.xls6746.TI_PAGE_1_REGISTERS.xls

  • 0 in reply to Pratik Mevada
    TI__Guru 57800 points

    Hi, Pratik,

    I tested your code and the EVM is working well, I see no issues with playback, but it is worth to mention that the recording function is not configured. This discards any issue with the routing configuration, so it is possible the problem is related to the clock settings.

    In general, the EVM should work fine with any MCLK as long as the correct clock and motherboard settings are done. one thing to note is that we recommend to use the same MCLK that is used by the processor to generate the I²S clocks, Is this the case for your application?. When using an external 24MHz clock, what is the configuration used on the SW2 of USB-MODEVM and where are you connecting the external clock?. Can you please share the exact clock conditions of your board and processor?.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Prodigy 60 points
    Hi

    In our case, 24 MHz MCLK is generated by crystal not by processor.
    I have connected External clock to P22(pin no: 17) and SW2 configuration is 2,4,5 are off and remaining are on.

    Thanks
    Pratik
  • 0 in reply to Pratik Mevada
    TI__Guru 57800 points

    Hi, Pratik,

    Thanks for the feedback. If the master clock comes from a crystal, I assume the I²S master of the bus would be the AIC3204, right?. If so, some considerations should be taken to generate BCLK and WCLK.  If the codec is not the master, the problem might be that there is no synchronization between MCLK and the I²S clocks from he processor. When the processor is the master of the I²S bus, it may be possible to use the bit clock to generate the internal clocks of the codec instead of the MCLK. Can you please share the frequency of the I²S clocks sent by your processor if it is the master of the bus?. 

    Please consider that In the EVM, the AIC3204 is slave to the USB-I²S bridge, so when testing with a different processor, the AIC3204 expects to be a slave device when using the scripts from the GUI.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Prodigy 60 points
    Hi,

    In our case, codec is not master.
    When i have used MCLK from EVM and other clock is generated by processor side, there is no issue of synchronization of MCLK and I2S clock and capture or playback is working. while using crystal's MCLK clock i am not able capture or playback.
    I2S frequency are,
    WCLK: 48 KHZ
    BCLK : 1.5 MHz

    Thanks,
    Pratik
  • 0 in reply to Pratik Mevada
    TI__Guru 57800 points

    Hi, Pratik,

    Thanks for the feedback. It is strange that you are not experiencing issues with the synchronization. From your code, the clock settings are fine when a MCLK of 24MHz is provided, can you please clarify if the code is the same for the test with the EVM?.

    From your test, how are you connecting the Crystal to the EVM?. It is  strange that you are unable to playback/capture audio, you should be able to get something out from the device even if the clock settings are wrong. One thing to double check is if the MCLK clock is valid on the codec side.

    One thing to try is to use the BCLK of your processor instead of MCLK from crystal to generate the internal clocks to see if the device is able to capture and playback audio. Please refer to below code as reference.

    ###########################################################
    # Clock configuration of AIC3204
    # BCLK = 1.536MHz
    # Sampling Rate = 48KHz
    ###########################################################

    w 30 04 07 # CODEC_CLKIN = PLL_CLK, PLL_CLKIN = BCLK
    w 30 05 92 # P = 1, R = 2, PLL ON
    w 30 06 1E # J = 30
    w 30 07 00 # D = 0
    w 30 08 00 # D = 0
    w 30 12 85 # NADC = 5
    w 30 13 83 # MADC = 3
    w 30 14 80 # AOSR = 128
    w 30 0B 85 # NDAC = 5
    w 30 0C 83 # MDAC = 3
    w 30 0D 80 # DOSR = 128

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer