TLV320ADC3101: TLV320ADC3101: How to configuration ADC3101 for Master mode in mclk 25M?

Hi, Li,

The ADC3101 has a flexible clock configuration and it is posible to configure it as the I²S Master. For this, both WCLK and BCLK should be configured as outputs with Register 27 of Page 0. The internal PLL should be used as 25MHz is not a standard audio MCLK frequency, the dividers combined with the PLL should be set to determine the required sampling rate. One thing to mention is that the BCLK divider should be enabled and configured properly to see the WCLK and BCLK outputs. 

Please refer to below example to configure the ADC3101 as the I²S master with a sampling rate of 44.1KHz. 

###########################################################
# Clock configuration
# Master Mode
# MCLK as PLL input
# MCLK = 25MHz
# BCLK = 2.8224MHz = 32×Fs
# WCLK = 44.1KHz = Fs
###########################################################

w 30 1B 0C # I²S format, 16-bit data, Master mode
w 30 04 03 # CODEC_CLKIN = PLL_CLK, PLL_CLKIN = MCLK
w 30 05 A1 # P=2, R=1, PLL ON
w 30 06 08 # J=8
w 30 07 05 # D=1285
w 30 08 05 # D=1285
w 30 12 89 # NADC = 9
w 30 13 82 # MADC = 2
w 30 14 80 # AOSR = 128
w 30 1E 88 # BCLK Divider = ADC_CLK/8, ON

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer