This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLV320AIC3120: No audio output

Part Number: TLV320AIC3120
Hi ,
I am t using TLV320AIC3120,
but I am getting faint click sound which is hardly audible, but I need longer beep sound. 
I need this EVM for BEEP generation only, I am not using I2S, just configuring Registers with I2C,

 
 Configuration which i have done is written below

 can you help me out on this,



#Select Page 0 w 30 00 00 # PLL_CLKIN = MCLK, CODEC_CLKIN = MCLK ######## MCLK=1 MHz w 30 04 03 & #0x07
# r=1,p=1;
w 30 05 92
# j=32
w 06 10
# D=0
w 07 00
w 08 00


# DAC Instruction set PRB_P25
w 30 3C 19



# NDAC ON div=1
w 30 0B 82
# MDAC ON div=2
w 30 0C 84
# DOSR = 144
w 30 0D  00
w 30 0E  90

# DAC Volume -0 dB
w 30 41 30

# DAC mute off
w 30 40 04
# DAC power up
w 30 3F 80
w 30 24 00
w 30 25 90

# Select Page 1 w 30 00 01 # Class d driver power up w 30 20 86
#DAC routed to mixer amp
w 30 23 40 # Class D route enable w 30 26 00 # Class D output driver mute off w 30 2A 1C ####Fs=50 Khz, Fin=1kHz. # Select Page 0 w 30 00 00 # Beep length=004E20 w 30 49 00 w 30 4A 4E w 30 4B 20 # sin wave coeffi=1008 w 30 4C 10 w 30 4D 08 # cos wave coeffi=7EFD w 30 4E 7E w 30 4F FD # Beep generate 0 db w 30 47 80






Thanks,
Zanza
  • Zanza,

    Redo the PLL and Divider settings, Processing block 25 is a resource heavy process flow. The resource class is 12.

    typically you should have it set up so MDAC * DOSR / 32 ≥ RC right now that is not the case for you.

    Are you providing any BCLK or wCLK at all?

    best regards,
    -Steve Wilson
  • Hi Steve,
    I have done this changes in pLL division
    # PLL_CLKIN = MCLK, CODEC_CLKIN = MCLK
    ######## MCLK=1 MHz
    w 30 04 03
    # r=1,p=1;
    w 30 05 91
    # j=48
    w 06 30
    # D=0
    w 07 00
    w 08 00

    # NDAC ON div=1
    w 30 0B 82
    # MDAC ON div=2
    w 30 0C 84
    # DOSR = 128
    w 30 0D 00
    w 30 0E 80

    And I am using MCLK as PLL clk not providing any BCLK or wCLK .

    Thanks,
    Zanza
  • Zanza,

    you will need to provide a few bclk cycles at the very least. I recommend running the device in master mode (set BCLK and WCLK to outputs)

    This will provide the kickstart the internal processing block needs to run.

    best regards,
    -Steve Wilson