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AIC3101 CC8520
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Related Posts

  • Forum Post: AIC3101 and CC8520

    Mike Wahler
    Greetings: I'm wanting to try the AIC3101 chip with the Anaren A8520 transceiver (uses TI CC8520). The 3101 datasheet lists four part numbers: TLV320AIC3101IRHBR TLV320AIC3101IRHBT TLVAIC3101IRHBRG4 TLVAIC3101IRHBTG4 What are the differences among these part numbers? Also, for a one-way...
    on Mar 3, 2012

  • Forum Post: RE: aic3101 data does not appear to be synced to wclk

    Tom Dagostino
    I bypassed the PLL and had the clock go directly to the clock divider path with the same results. BCLK and WCLK look good and are sync'ed but the data is not. Thoughts?
    on Mar 12, 2013

  • Forum Post: RE: aic3101 data does not appear to be synced to wclk

    Tom Dagostino
    Well, that is what I thought also but it is definitely out of sync. If I trigger on WCLK and look at the data coming out of the DIR9001 I see the expected block of data framed by the states of WCLK. When I switch over to the AIC3101 and trigger on WCLK the data is spread all over the states of WCLK....
    on Mar 12, 2013

  • Forum Post: RE: aic3101 data does not appear to be synced to wclk

    Tom Dagostino
    This is data coming out of the AIC3101. When the DIR9001 is active the data for each channel (left or right) is in a small section of the states of WCLK. When the AIC3101 is driving data out the data is smeared over the entire window of WCLK. See attached.
    on Mar 13, 2013

  • Forum Post: RE: aic3101 data does not appear to be synced to wclk

    Tom Dagostino
    In both cased the upper trace is the data out and the lower trace is WCLK. In the first picture the data is coming from the DIR9001 and you can clearly see the data is framed nicely by WCLK and takes up the appropriate amount of time. In the other picture from the AIC3101 the data is spread all over...
    on Mar 14, 2013

  • Forum Post: RE: aic3101 data does not appear to be synced to wclk

    Tom Dagostino
    Here is the present setup. I've done some experiments to try different setting to see what I get and you can see that in the code. w 30 00 00 #sets page 0 w 30 02 00 w 30 03 91 #enable PLL, P=1, Ignore the Q value w 30 04 1C #J=7 # w 30 04 20 #J=8 w 30 05 52 #D=5264 w 30 06 40 #D...
    on Mar 14, 2013

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