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DAC32 interface to SSI port
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Q: DAC32 WCLK Questions
Trying to interface the DAC32 to an SSI port on a Stellaris uC.
This is a native 16bit interface so having problems making a glueless connections.
- If the DAC32 is a slave (MCLK driven by Stellaris 12.5Mhz clock as well), how close does WCLK needbe to 44.1 Khz. before having problems with the digital audio interface? WCLK will have approximately.02% error to 44.1Khz.
- Does the DAC Re-Sync (D2 in Control Register B) help in this case?
- If the DAC32 is in DSP mode, what will it do if it gets a pulse on WCLK right after the left channel SDIN (middle of frame)?The Stellaris team has reported some codecs simply ignore this.
A: Re: DAC32 WCLK Questions
WCLK should be at exactly the sample rate that they want to run at. They can use the internal PLL to derive the Fs Clock from their MCLK. The actual sample rate is set by MCLK, WCLK and BCLK simply clock the data in. Since there is no buffer on the DAC32, if WCLK doesn't match the sample rate set by WCLK and the register settings (PLL etc...), they will either mis samples or clock samples in twice. In either case, you can end up with audible artifacts.
I would recommend using the PLL to match Fs to WCLK exactly, or setting the DAC32 as the master.
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