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Q: Readback DIR Sample Rate from SRC4392
How can I read the sample rate from the SRC4392?
Q: Re: Readback DIR Sample Rate from SRC4392
Register address 0x13 on Register Page 0 contains two status bits, RXCKR0 and RXCKR1. These bits can be used to indicate that the DIR input sampling rate falls within a range of rates as shown below.
if RXCKR[1:0] = 0x00, then the DIR input sampling rate is indeterminate (the DIR may be unlocked or tracking a change in rate).
If RXCKR[1:0] = 0x01, then the DIR input sampling rate is greater than 108kHz and less than or equal to 216kHz.
If RXCKR[1:0] = 0x10, then the DIR input sampling rate is equal to or greater than 54kHz and less than 108kHz.
If RXCKR[1:0] = 0x11, then the DIR input sampling rate is equal to or greater than 20kHz and less than 54kHz.
Ideally, these bits should be read back when the DIR is locked to the AES3 or S/PDIF input stream.