TI E2E Community
/etc... Data Converters
/etc... Data Converters Forum
ADS8327 SPI mode
datasheet of the ADS8327 says that ist supports CPOL=0,CPHA=1 (should be SPI mode 1) and CPOL=1,CPHA=0 (should be SPI mode 2). In both of this modes, the master should sample the data at the falling clock edge. But the scope tells me, that the ADS changes its SDO line at the falling edge (with a delay of max 16ns). So this indicates I should sample at the rising clock edge, right. Is the datasheet wrong or am I?
Neither you nor the data sheet are wrong. Is it safe to assume that you are running the ADS8327 with a relatively slow SCLK? The SDO does actually get released with the falling SCLK edge (with a fixed delay) in order to support the high speed serial interface. If you were running the clock at the 33MHz maximum speed listed in the data sheet, that 16ns delay you see would make the phase relationship look 'normal'.
I got it working.
Great to hear! Thanks for letting us know.
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.