Hi,
Currently we are using DAC101S101 with MSP430G2553.
We need some confirmation about the DAC's SPI communication.
According to the datasheet "A write sequence begins by bringing the SYNC line low Once SYNC is low,
the data on the DIN line is clocked into the 16-bit serial input register on the falling edges of SCLK"
We actually tried with MSP430 and DAC,we used GPIO pin as the SYNC singnal from MSP430(running at 16MHz).
After the SYNC signal is held LOW, the clock from the MSP430(Master) starts after 500ns delay as shown below.
We would like to know if this delay between the SYNC signal and the SPI clock is allowed
and if there are any possible problem if there is a delay between the SYNC line and the SCLK.
Please let me know if there is any timing constraint between
SYNC line low and the first clock edge.
Regards
Prad