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How can I define sampling rate of DAC ?

Kenji Itoh
Intellectual 420 points
Other Parts Discussed in Thread: DAC9881

Dear members. 

 I can't find definition sampling rate(fDac) of DAC in any data sheet and other web site. 

Please teach me definition as equation.    

      eg;   fDAC = xxx /*** 

 regards,

Kenji Itoh

  • 0
    TI__Mastermind 46290 points

    Kenji,

    This depends on whether you require the output to fully settle or not. You can write the a give DAC as quickly as the digital interface allows you to, but the output may not settle.

    If you want the output to settle, the update rate is simply the settling time specification.

    Here's a blog post if you'd like to read more about settling time:

    http://e2e.ti.com/blogs_/b/analogwire/archive/2013/08/26/dac-essentials-understanding-your-dac-39-s-speed-limit.aspx

  • 0 in reply to Kevin Duke
    Intellectual 420 points

    Kevin-san

     Thanks your reply.   I understand settling time in DAC. 

    But I want to answer  how  set up equation sample rate of DAC in datasheet.

    For example,   settling time of DAC9881  is 5 micro sec.  But it's has no sample  rate (fDAC).  

     And  my customer asked sample rate (fDAC) of DAC9881. 

     Regards,

    Kenji itoh

  • 0 in reply to Kenji Itoh
    TI__Mastermind 46290 points

    Kenji,

    An ADC has an analog input and a digital output and the conversion process takes a finite amount of time to deliver the digital output word, which is provided in all ADC datasheets as the sampling rate. 

    A DAC, on the other hand, has a digital input and an analog output. Our result is analog which has an infinite number of possible states, as compared to the finite number of states of a digital output. In this case the output is updated immediately once the digital word has been latched to the DAC data register, however it takes some time for the analog output to slew and settle to the value it was programmed to. In this case the datasheet provides the worst-case amount of time it would take for the DAC to settle over a very wide step and settle within some specified error band, usually 1/2 the LSB weight.

    This means "update-rate" or sample rate (sample rate is really a bad name for this mechanic related to a DAC - we're not really sampling anything. We're writing. Updating) for a DAC has some room for interpretation, unlike the ADC that delivers a very specific result with very specific timing. In one case it could be defined by what is the maximum rate with which we may write to a given part. In this case the update rate is defined by the digital interface timing requirements. In the other case, if we required fully settled analog outputs, the sampling rate is defined by the settling time.

    Does this make sense?