We have some questions regarding TXB0108 and TLC5540I. This is posted in high speed data converters forum. The doubts and replies are given below.
- Can I use TXB0108 device to level translate signals between ADC and FPGA?
Reply: I am not an expert on the TXB0108, but based on the datasheet and specified bit rates, yes. You may want to post to the interface forum for confirmation. - Can I use same TXB0108 for CLK signal also?Let us know what is jitter and other parameters need to take care for ADC CLK?
Reply: In terms of the ADC clk, you want to avoid jitter of the clock edge. My concern here would be with the bidirectional nature of theTXB0108. I'm not sure if this would cause distortion (duty cycle) of the clock signal and if it does if it would be consistent. I would be more comfortable using a fixed direction level translator, but I have no data to prove the TXB0108 would or would not work. For a fixed translator, it will add jitter, but the FPGA is likely the limiting factor here. This is also an 8-bit ADC, so noise performance will be limited by quantization noise. - Our application is required to maintain skew between channels,what is the device to device skew of TXB0108 and TLC5540I?
Reply: The only data we have on the TLC5540 is what's in the datasheet. I see only a typical spec for sampling delay, but min and max numbers for clock to data out delay (tpd). Skew will be minimized if all parts stay near the same temperature and power supplies have tight tolerance. TXB0108 is covered by a different group, so you will need to post to the interface forum. - Our design required reference voltage of 3.2V. I used external 289 ohms resistor to generate the same.Is that correct way to generate?
Reply: Your reference setup should work. Your input signal should swing between 0 and 3.2V with this setup.
Please clarify about first,second and third.
Regards,
Matt Guibord
