I am trying to interface PIC18F4550 with ADS1298 and as of now I just need to receive the Device ID right from ADS1298 to ensure the SPI has been established.
I am attaching my code for PIC18F4550 along.
I don't understand what's going wrong.
I followed the instructions given in the ADS1298 datasheet and referred to various sample codes to check if the flow of instructions is correct.
But I am not getting the desired output.
I also checked separately if the SPI for PIC is working and that was working fine.
So please help me find what exactly is going wrong in the code for ADS1298.
All I want to do as of now is receive the device ID from ADS1298 and display it on PORTD pins.
/*
* File: ecgcode1.c
* Author: SONY
*
* Created on 4 January, 2015, 12:02 PM
*/
//#include <stdio.h>
//#include <stdlib.h>
#include <xc.h>
#include <sw_spi.h>
#include <delays.h>
// PIC18F4550 Configuration Bit Settings
// CONFIG1L
#pragma config PLLDIV = 0 // PLL Prescaler Selection bits (Divide by 5 (20 MHz oscillator input))
#pragma config CPUDIV = 0// System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])
#pragma config USBDIV = 0 // USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes from the 96 MHz PLL divided by 2)
// CONFIG1H
#pragma config FOSC = 0b1001 // Internal oscillator, CLKO function on RA6, EC used by USB (INTCKO)
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = ON // Internal/External Oscillator Switchover bit (Oscillator Switchover mode enabled)
// CONFIG2L
#pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled)
#pragma config BOR = ON // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
#pragma config BORV = 3 // Brown-out Reset Voltage bits (Minimum setting)
#pragma config VREGEN = ON // USB Voltage Regulator Enable bit (USB voltage regulator enabled)
// CONFIG2H
#pragma config WDT = OFF // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
#pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)
// CONFIG3H
#pragma config CCP2MX = ON // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = OFF // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
#pragma config LPT1OSC = OFF // Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)
#pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)
// CONFIG4L
#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = OFF // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
#pragma config ICPRT = OFF // Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit (ICPORT disabled)
#pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
// CONFIG5L
#pragma config CP0 = OFF // Code Protection bit (Block 0 (000800-001FFFh) is not code-protected)
#pragma config CP1 = OFF // Code Protection bit (Block 1 (002000-003FFFh) is not code-protected)
#pragma config CP2 = OFF // Code Protection bit (Block 2 (004000-005FFFh) is not code-protected)
#pragma config CP3 = OFF // Code Protection bit (Block 3 (006000-007FFFh) is not code-protected)
// CONFIG5H
#pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected)
#pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM is not code-protected)
// CONFIG6L
#pragma config WRT0 = OFF // Write Protection bit (Block 0 (000800-001FFFh) is not write-protected)
#pragma config WRT1 = OFF // Write Protection bit (Block 1 (002000-003FFFh) is not write-protected)
#pragma config WRT2 = OFF // Write Protection bit (Block 2 (004000-005FFFh) is not write-protected)
#pragma config WRT3 = OFF // Write Protection bit (Block 3 (006000-007FFFh) is not write-protected)
// CONFIG6H
#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) are not write-protected)
#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected)
#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM is not write-protected)
// CONFIG7L
#pragma config EBTR0 = OFF // Table Read Protection bit (Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF // Table Read Protection bit (Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF // Table Read Protection bit (Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF // Table Read Protection bit (Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks)
// CONFIG7H
#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) is not protected from table reads executed in other blocks)
#define _XTAL_FREQ 2000000
// Device Setting Read Only
// Global Setting across channels
#define CONFIG1 0x01
#define CONFIG2 0x02
#define CONFIG3 0x03
#define LOFF 0x04
// Channel specific settings
#define CH1SET 0x05
#define CH2SET 0x06
#define CH3SET 0x07
#define CH4SET 0x08
#define CH5SET 0x09
#define CH6SET 0x0A
#define CH7SET 0x0B
#define CH8SET 0x0C
#define RLD_SENSP 0x0D
#define RLD_SENSN 0x0E
#define LOFF_SENSP 0x0F
#define LOFF_SENSN 0x10
#define LOFF_FLIP 0x11
//Lead Off Status Registers (Read Only)
#define LOFF_STATP 0x12
#define LOFF_STATN 0x13
//GPIO and other registers
#define GPIO 0x14
#define PACE 0x15
#define RESP 0x16
#define CONFIG4 0x17
#define WCT1 0x18
#define WCT2 0x19
#define DevID 0b10010010
// opcode commands
#define WAKEUP 0x02
#define STANDBY 0x04
#define RESETr 0x06
#define START 0x08
#define STOP 0x0A
#define RDATAC 0x10
#define SDATAC 0x11
#define RDATA 0x12
void delay_millisec(unsigned int X);
void SPI_Write(unsigned char addr,unsigned char data);
unsigned char SPI_Read(unsigned char addr);
void OPCODE_Write(unsigned char code);
int main(void) {
OSCCON = 0b01011111; // 2Mhz internal clock frequency
ADCON1bits.PCFG = 0b0000; // All pins configured as digital
TRISBbits.RB0 = 1; // SDI configured as input
TRISBbits.RB1 = 0; // SCLK configured as output
TRISCbits.RC7 = 0; // SDO configured as output
TRISCbits.RC6 = 0; // To be connected to SS of slave device.
// TRISCbits.RC2 = 0; // connected to RESET pin of ADS1298
TRISD = 0x00; // port D configured as output
LATD = 0x00; // all outputs set to 0;
unsigned char ID = 0;
// SPI mode configuration
SSPCON1bits.SSPEN = 0; // Disable serial port
SSPCON1bits.SSPM = 0b0000; // SPI master mode , clock = Fosc/4
SSPSTATbits.SMP = 0; //
SSPSTATbits.CKE = 0;
SSPCON1bits.CKP = 0; // Idle state for clock is low level
SSPCON1bits.SSPEN = 1;
/*
LATCbits.LATC2 = 0;
__delay_ms(1);
LATCbits.LATC2 = 1;
*/
delay_millisec(820);
OPCODE_Write(RESETr);
__delay_us(9);
OPCODE_Write(STOP);
OPCODE_Write(SDATAC);
__delay_us(2);
SPI_Write(CONFIG3, 0xC0);
SPI_Write(CONFIG1, 0x86);
SPI_Write(CONFIG2, 0x00);
SPI_Write(CH1SET, 0x01);
SPI_Write(CH2SET, 0x01);
SPI_Write(CH3SET, 0x01);
SPI_Write(CH4SET, 0x01);
SPI_Write(CH5SET, 0x01);
SPI_Write(CH6SET, 0x01);
SPI_Write(CH7SET, 0x01);
SPI_Write(CH8SET, 0x01);
ID = SPI_Read(0x00);
//LATD = ID;
while (1)
{
//ID = SPI_Read(0x00);
LATD = ID;
}
// return (EXIT_SUCCESS);
}
void delay_millisec(unsigned int X)
{
do
{
X--;
__delay_ms(1);
}
while(X > 0);
}
void SPI_Write(unsigned char addr,unsigned char data)
{
// Activate the SS SPI Select pin
LATCbits.LATC6 = 0;
// Send the address of the register to be accessed
SSPBUF = (0x40|addr);
// Wait for Data Transmit/Receipt complete
while(!SSPSTATbits.BF);
// Delay of 4 tCLKs after every transfer. Refer pg40 of ads1298 datasheet
__delay_us(2);
// One register at a time
SSPBUF = 0x00;
// Wait for Data Transmit/Receipt complete
while(!SSPSTATbits.BF);
// Delay of 4 tCLKs after every transfer. Refer pg40 of ads1298 datasheet
__delay_us(2);
// Write data
SSPBUF = data;
// Wait for Data Transmit/Receipt complete
while(!SSPSTATbits.BF);
// Delay of 4 tCLKs after every transfer. Refer pg40 of ads1298 datasheet
__delay_us(2);
// CS pin is not active
LATCbits.LATC6 = 1;
}
unsigned char SPI_Read(unsigned char addr)
{
// Activate the SS SPI Select pin
LATCbits.LATC6 = 0;
// Send address of the register to be accessed
SSPBUF = (0x20|addr);
// Wait for Data Transmit/Receipt complete
while(!SSPSTATbits.BF);
// Delay of 4 tCLKs after every transfer. Refer pg40 of ads1298 datasheet
__delay_us(2);
// One register at a time
SSPBUF = 0x00;
// Wait for Data Transmit/Receipt complete
while(!SSPSTATbits.BF);
// Delay of 4 tCLKs after every transfer. Refer pg40 of ads1298 datasheet
__delay_us(2);
// Send dummy variable
SSPBUF = 0x00;
// Delay of 8 tCLKs after every transfer
__delay_us(4);
// Wait for Data Transmit/Receipt complete
while(!SSPSTATbits.BF);
// Delay of 4 tCLKs after every transfer. Refer pg40 of ads1298 datasheet
__delay_us(2);
// Delay of 4 tCLKs before CS goes high. Refer pg15 of ads1298 datasheet
__delay_us(2);
// CS pin is not active
LATCbits.LATC6 = 1;
return(SSPBUF);
}
void OPCODE_Write(unsigned char code)
{
// Activate the SS SPI Select pin
LATCbits.LATC6 = 0;
// Send the OPCODE
SSPBUF = code;
// Wait for Data Transmit/Receipt complete
while(!SSPSTATbits.BF);
// Delay of 4 tCLKs after every transfer. Refer pg40 of ads1298 datasheet
__delay_us(2);
// Delay of 4 tCLKs before CS goes high. Refer pg15 of ads1298 datasheet
__delay_us(2);
// CS pin is not active
LATCbits.LATC6 = 1;
}