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ADS131 Daisy Chain slave (2-the) ADC configuration issue

Koenraad Vanderschaeve
Prodigy 70 points
Other Parts Discussed in Thread: ADS131E08, ADS131E04

Hi,

I have a board with a daisy chained ADS131E04 master, first ADC, and ADS131E08 as slave, 2-the ADC. When i power up the board (cold reset), the 2-the ADC never initializes OK to 4Kbps sampling mode. I need an extra warm master reset to the whole board and then the 2-the ADC configures OK. I checked the POR sequence described in the ADS131 datasheet and also the sequence of 5V and 3V3 en all is following the specs. 

All ideas welcome...

Regards,

Koenraad

  • 0
    TI__Mastermind 43915 points
    Hi Koenraad,
    We have seen things like this happen when Figure 23 timing is not being met. Look at the slew rate on the VCAP1 pin on the second device to see how long the device takes to slew. We typically recommend a RESET pulse following VCAP1 meeting 1.1V to ensure that the default settings are properly loaded to the converter before programming begins. An interesting picture would be to plot VCAP1 of the first device and VCAP1 of the second device to see if there is any variance in the ramp rates.
    Thanks,Tony
  • 0 in reply to Tony Calabria
    Prodigy 70 points

    Hi Tony,

    Thanks for the reply but unfortunately, no , that is not the case. VCAP1 on both devices is the same and the reset pulse comes miles after the VCAP1 reaches 1.1 V on both devices...

    Koen

  • 0 in reply to Koenraad Vanderschaeve
    Prodigy 70 points

    I think i found the problem. I use the internal clock on the master ADC and the clk pin (out) on the first adc is used as external clock for the slave adc. I wait a couple of seconds for the internal clock to settle before continue with the configuration. After that, i write  the config1 register first to enable the clk pin on the master device. I wait a couple of ms to let ADC 1 to output the clock and then i write the config1 again to configure the slave ADC (in the meantime the clk was present). But that only works when i warm reset the board and that probably because the external clock was already present on the slave device.  When the board was powercycled, the slave ADC was never configured properly. So i added a much larger delay before configuring the slave ADC (2 seconds) and it works...

    I followed flowchart on page 33 of the datasheet but it is not clear how much time you need to wait when applying an external clock to use the ADC.