Error in code DAC8750

Genius 3300 points

Other Parts Discussed in Thread: DAC8750

1. I have written code for DAC8750.

I am successfully able to write DAC data register & I correctly read its value back by read operation.

But problem is in actual the setting don't take effect, even though data can be read back correctly.

Actual settings only take effect wen I power on/off the complete circuit

1. Dvdd = 3.3V. Avdd = 11V. Rload = 100ohm. But Avdd & DVDD are applied at same time.

2. IS there any sample code for DAC8750

3. Code algo is:

void dac8750(void)
{
/* configure pin  */
	alarm_openDrain_input();
	clear_output_low();
	latch_output_high();
	SPI_Mode0();

/* write control register */
	latch_output_low();
	delay_us(10);
    send_spi_byte(0x55);
    send_spi_byte(0x10);
    send_spi_byte(0x05);  
    delay_us(10);    
    latch_output_high();  
    delay_us(100);    
	
/* write dac register */
	latch_output_low();
    delay_us(10);
    send_spi_byte(0x01);
    send_spi_byte(0x7f);
    send_spi_byte(0xff); 
    delay_us(10);    
    latch_output_high();  
    delay_us(100);  	

/* read dac data */    
	latch_output_low();
    delay_us(10);
    send_spi_byte(0x02);
    send_spi_byte(0x00);
    send_spi_byte(0x01); 
    delay_us(10);    
    latch_output_high();    
    delay_us(100);   
    
	latch_output_low();
    delay_us(10);
    send_spi_byte(0x00);
    data = receive_spi_byte(0x00);              /* at this point I read correct dac register values */
    data1 = receive_spi_byte(0x00); 
    delay_us(10);    
    latch_output_high();      
    delay_us(100);   

}

over 8 years ago

0 Kevin Duke over 8 years ago

TI__Mastermind 46290 points

Vindhyachal,

Is it safe to assume that you are working with the same schematic that we reviewed previously? Could you provide an oscilloscope capture of LATCH, SDI, and SCLK (from DAC8750's perspective) during a write sequence and LATCH, SDO, and SCLK on a read sequence? I cannot extrapolate timing, clock phase, or clock polarity from the code snippet which would be good to check for this issue.

Some MSP430 sample code is attached:

6013.DAC8760_Interface.zip

0 VT over 8 years ago in reply to Kevin Duke

Genius 3300 points

Hi kevin,

1. yes the ckt was as we had discussed here:

2. I have attached two pics. Probe is at 10x. SPI speed is 1Mhz. In actual I will use 15Mhz.

Pic1: SPI clock & SPI data (0x55)

Pic2: Latch with clock. (three bytes are sent)

pic.pdf

0 VT over 8 years ago in reply to VT

Genius 3300 points

moreover, i have been to read back correct data, so I think communication is ok.
e.g when i write certain value in data register, I have been able to read back it correctly. Same is case with control register.

But it don't take effect immediately, even though in control register output is enabled.

0 VT over 8 years ago in reply to VT

Genius 3300 points

any update on it Kevin Duke .

I m still not able to solve this issue.

0 Kevin Duke over 8 years ago in reply to VT

TI__Mastermind 46290 points

Vindhyachal,

I am traveling abroad at the moment with limited access to the internet. I will look into the images you shared as soon as I can.

0 Matthew Sauceda over 8 years ago in reply to VT

TI__Genius 11750 points

Howdy Vindhyachal Takniki,

Kevin is currently out traveling at the moment, but I may be able to assist you with your questions.

-Can you provide an oscilloscope capture or status of the LATCH signal during communication?

Regards,
Matt

0 VT over 8 years ago in reply to Matthew Sauceda

Genius 3300 points

Matt,

It is attached in post#3.

0 Kevin Duke over 8 years ago

TI__Mastermind 46290 points

Vindhyachal,

Thank you very much for your patience. I am back in my office so we should be able to communicate much more quickly now.

From the scope captures you've provided it certainly appears that you are adhering to the correct clock phase and polarity settings. I am a little confused, though, because the voltage magnitude shown on your plots is 100mV and 200mV per division for each yellow and blue channels, respectively. So it appears that amplitude of all of the digital signals is only 400mV, which wouldn't be sufficient to actually trigger a logic high using 3.3V DVDD.

I have another question from your original post.

Vindhyachal Takniki said:
Actual settings only take effect wen I power on/off the complete circuit

What does this mean?

0 VT over 8 years ago in reply to Kevin Duke

Genius 3300 points

1. Probe was on 10x that's why it had such small amplitude. Multiply by 10 to get actual amplitude.
2. If I put new code to master MCU like I have changed current setting from 4mA out to 5mA out.
Now at this point setting don't take effect. Even though on reading data back from DAC gives correct result. (That's is most strangest part )
Now if I power cycle the MCU again setting takes effect now.

0 Kevin Duke over 8 years ago in reply to VT

TI__Mastermind 46290 points

Vindhyachal,

Just to make sure I understand - in your example where you change the current output setting from 4mA to 5mA the output does not respond. However, once the MCU has power cycled the output updates from 4mA to 5mA? What happens to the digital lines when the MCU power cycles? I would assume you get a falling edge followed by a rising edge on LATCH? For the sake of experiment you might try replicating whatever logical patterns you see on power-cycle to see if we can reason-out why the power cycle causes the output to update.

On power-up, what are the first couple of write sequences you apply to the part? What happens to the digital I/O lines as the MCU powers up?

0 VT over 8 years ago in reply to Kevin Duke

Genius 3300 points

Sry, I not at lab.
Will be back in few days & will see

0 Kevin Duke over 8 years ago in reply to VT

TI__Mastermind 46290 points

Vindhyachal,

Any updates on this?

0 VT over 8 years ago in reply to Kevin Duke

Genius 3300 points

Hi kevin,

sry for late reply. Actually i am off for some training.
Will reply when i try it back.

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Error in code DAC8750