This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Anti-Alias Filter for Single-Ended Input (ref: ADS8866 datasheet)

Other Parts Discussed in Thread: ADS8866

Hi,

I'd like to ask about the filter to be used on a differential ADC operating on a single-ended signal.

Figure 56 of ADS8866 datasheet shows a recommended filter.  This applies a capacitor across the ADC inputs and in-line resistors from the signal to the positive (non-inverting) input and from ground to the negative input.

It seems to me that this topology does not attenuate the common mode signal presented to the ADC.  (I agree with the -3dB formula shown for the differential signal.)  Above the -3dB frequency, the common mode signal will exceed the desired differential signal, and will need to be rejected by the ADC.

The ADS8866 datasheet doesn't show, (unless I've over-looked it), CMRR except at DC.  The common mode signal may be a problem - not sure.

Would it be better to connect the negative input directly to signal ground?  Or does this increase distortion due to un-matched input impedances?

Or should the negative ADC input be driven by ground through a parallel R-C network matching the positive input's impedance?

Note that the datasheet's next diagram, Figure 57, does show the negative input directly grounded, so I guess it's not fatal!

Any wisdom on this appreciated.

Thanks and regards,

Mark

  • Mark,

    1. You are correct. The capacitor arrangement does not help with common mode noise rejection. However, this ADC is really a “pseudo-differential” input. By that I mean that one input is really a single ended input signal, and the other is a “ground sense” input. That is, the negative input can only accept signals very near ground (AINN range = +/-0.1V). In this kind of arrangement you would not expect to pick up a large AC common mode signal as the negative input is line is normally very short and grounded.

    2. The main purpose of the capacitor, Cfilt, in figure 56 is to “reduce the sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold capacitors”. The data sheet text talks a lot about antialiasing and noise filtering, but this is really of secondary importance. In fact, the cutoff frequency of this filter is about 6MHz so it doesn’t actually act as an antialiasing filter as the sampling rate is 100ksps. I apologize for the confusion here.

    3. For best performance you should match the impedance in both the positive and negative input (AINP and AINN). The negative input is just sensing ground currents.

    4. Figure 56, is a proven measured configuration. I would just use this configuration.

    Let me know if this helps or if you have additional questions.

  • OK, thanks Art.

    Regards,


    Mark