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ADS8556 Eval Board in HW mode, parallel xfer with misaligned channel reads

Allen Wirt
Prodigy 30 points
Other Parts Discussed in Thread: ADS8556

Using the ADS8556 Eval module in default HW mode and parallel xfer of Words, I am observing DB13 as a representative of the data.  I have B1 set to 4VDC and the remaining 5 channels at 1VDC.  I should see the 4th of 6 channel reads as a high and the others as low for this bit in the xfer.  What I actually see is a high at B1's location 60% of the time, but the high is sometimes at B0 and sometimes at C0.  I am not pushing the timing envelope, but I am attaching a timing diagram.  Any reason that the channel alignment can bounce around? 

I have all CONV tied together. STBY is tied high, RESET is tied low. AVdd=5V, BVdd=3.3V, HVdd=8V, HVss=-8V.

  • 0
    Prodigy 30 points
    I think the gotcha is that you better have a solid ground scheme between CPU board and ADC eval board because noise bounces on the RD line could cause false triggers to the ADC sequential channel output in parallel mode.
  • 0 in reply to Allen Wirt
    TI__Guru* 92715 points
    Allen,


    I'd just noticed this post in this forum. Was the problem caused by ground bouncing on your board? If so, I'll label this post closed.


    Joseph Wu
  • 0 in reply to Joseph Wu
    Prodigy 30 points

    I thought that might be contributing (it seemed possible), so I improved the connections between my two development platform boards (one for CPU and the other the ADS8556).  I am not so sure it is a noisy RD line.  Varying one input level impacts the others readings randomly.  I am still studying other post data regarding mis-reads and will move to a single-board layout with shorter traces to eliminate distance concerns.  That layout will delay further progress on this issue.