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ADS124S08 SPI communication delays

Other Parts Discussed in Thread: ADS124S08

hello there,

I am facing some issue with the SPI communication with ADS124S08 with PIC18f45k22.

the SPI operates at a baud rate of 450k. and there is no problem getting converted data when CS to first clock pulse and last clock pulse to CS disable delay is 50ms.

the ADC is configured to operate in single shot mode. since we have different configuration on each channel, we configure the channel each time, send the start command and later read it. as I mentioned, all this works at higher SPI delays.

but when this delay is reduced to 10ms we see there is no response from ADS1240S.

for isolation we have an isolator(ADMU1401) on the SPI bus.

below is the sample code to control the CS with delay.

please feel free to ask any clarification.

/**/

#define CS_2_CLK_DLY 10

#define CLK_2_CS_DLY 10

/* CS enable */

VOID siospi_adc_cs_en(UINT8 chn)

{

/* is this ADC 1 ?*/  

if(chn < 0x02 )  

{ /* yes */  

 /*drive low, slave select 1(RA5)*/  

 LATA = LATA & 0xDF;  

}  

else

 {/* no */   

/*drive low, slave select 2 (RA2)*/   

LATA = LATA & 0xFB;   

}  

 /* set delay after cs and clk */

 f_sio_spi_to = SAT_FALSE;  

g_sio_spi_to_cnt = 0;  

g_sio_spi_to_lmt = CS_2_CLK_DLY; //10ms

 /* wait for delay */

 while (f_sio_spi_to == SAT_FALSE);

} /* siospi_adc_cs_en(), end*/

 

/* diable channel */

VOID siospi_adc_cs_ds(UINT8 chn)

{

/* delay after last bit read and cs low */  

f_sio_spi_to = SAT_FALSE;  

g_sio_spi_to_cnt = 0;  

g_sio_spi_to_lmt = CLK_2_CS_DLY; // 10ms    

/* wait for delay before cs disable from clk */  

while (f_sio_spi_to == SAT_FALSE);

 /* is this ADC 1 ?*/

 if(chn < 0x02 )  

{ /* yes */  

 /*drive high, deselec slave 1 (RA5)*/  

 LATA = LATA | 0x20;

 }  

else  

{   

/*drive high, deselec slave 2(RA2)*/   

LATA = LATA | 0x04;  

}  /* is this ADC 1 ?, end */

} /* spi_adc_cs_ds() end */

  • Rupesh,


    The easiest thing that would help is to use a logic analyzer to see what is happening in the SPI communication. With a logic analyzer, I'd get the /CS, SCLK, DIN, DOUT, and perhaps the /DRDY.

    If you don't have a logic analyzer, it might be sufficient to use an oscilloscope to grab the first four signals of that list. Or once you confirm the /CS, go back and re-take the shot to grab /DRDY so that you can see the indication that the ADC conversion is completed before you start trying to retrieve data.

    When you have some sort of problem with the digital communications, it really helps to look at the signals. It's often too hard to find the bug in code.


    Joseph Wu
  • Hi Rupesh,

    Joseph is correct.  It is best to analyze your communication using an external scope/analyzer.  The minimum delay period required is 20ns, so it is doubtful that you need any delay with respect to CS.  There will most likely be sufficient delay by just making the function call.

    What you are saying is if you have lots of delay the device will work respond.  Are you issuing some other request prior to the CS going low that will affect the communication?  For example, if you issue a RESET or try to communicate too soon after power-up you will have issues.

    So, along with the communications shots request, please send us a step by step process of what you are trying to do as well as the register settings.

    Thanks,

    Bob B

  • hello Joseph and Bob,

     

    Sorry for the delay in my response. We have found the problem. I will post the solution shortly after we fix it completely. hopefully in a day or 2.

    thank you for the pointers.

     

    regards

    Rupesh.

  • Rupesh,


    I'm glad you were able to find a solution. Thanks in advance for posting your solution. It always helps to get solution responses so that anyone else can benefit from it.


    Joseph Wu