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DDC264EVM: Verilog Firmware version of DDC264EVM

Part Number: DDC264EVM


I use the DDC264EVM. and I would like to use the Hardware trigger but:

1/ The datasheet and the REVISION board and the  Verilog_Firmware version of DDC264EVM don't match together.

- The version of the board is REV1 that we have bought.

- The datasheet of the DDC264EVM is REVA

- The revision of code source Verilog is REVB

2/ In the verilog code source, the "top_constraints_2.ucf" file is the Input-Output pin assigned of the FPGA and we do'nt recognize the location of the "HARDWARE_TRIG_IP" pin in this "top_constraints_2.ucf" file .

Please, can you give me some informations about that?

Thanks a lot for your help.

Best regards

Philippe Abbon