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ADS7807: ADS78xx Errata
Part Number: ADS7807
Customer has questions about ADS78xx.I got a schematic schematic around the ADS7807 from customers.
With this circuit configuration, Vana and Vdig are stable and data of ADC is read after 100 mS or more.At this time the voltage of R1in was 0.6V.When this phenomenon occurred, this value was 0x3FFB only for the first access.The Read value from the ADC should be around 0x8881 if it is normal.Can you find the cause of this phenomenon occurrence?
Thanks, Masami M.
This device has a configurable input range through the external resisters at pins1 R1in and 3 R2in, as shown in figure 7 in the datasheet and below. Withouth these external resisters, the device will not function as expected.
From the schematic, the customer is using a 1-5 V input, which means the 0-5V input range configuration would be best for them. Without hardware trim, the customer should implement the second circuit configuration.
They will need to add the external resisters highligheted and connect the input signal at the 100 ohm resisters at pin 3.
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In reply to Cynthia:
Thanks for your support.Since customer's circuit shares the same board design with other sensors, ±10V support is required.For this reason, the circuit configuration is created from the leftmost of the diagrams presented.Is limiting resistance necessary even in this case?Also, since there is no limiting resistor, can I understand that only the reading value of the first ADC leads to a phenomenon in which the reading value is greatly out of order?
If possible, please tell me why the first Read Data value goes wrong in the absence of limiting resistance.
In reply to Masami Michino:
I see, thank you for clarifying.
The external resistors are used to compensate for the offset and gain adjustments that occur internally, if the customer is fine with these present or plan to calibrate in software, the external resistors do not need to be implemented.
Keep in mind that on intial power up the parallel output will have unvalid data. Is the customer reading correct data at every read (R/C) pulse except the first one after initial power up?
If the customer could provide a scope shot with RC, CS, BYTE, and BUSY, I could look it over and make sure the timing is correct as well
Thanks for your support.Customers removed the reproduction environment, so there is no detail timing part.However, there is a schematic scope shot of the following.
When reproducing phenomena
Just to clarify, when you say "first read" do you mean after initial power up? When the device first gets powered up and changed to parallel mode, the output registers will not hold valid data and a dummy read will be needed, this is expected behavior.
Also, if device has been powered down it will only hold valid information if the output had not shifted out through the serial port already.
The timing looks good from what I can see. As the customer continous with thier design, I would like to point out the timing diagram in figure 2 of the datasheet. In parallel, this device only has valid data when RC is high and CS is held low. This means that CS can be hardwired to ground, and conversion results can be read only using RC. this is only an option, they can continue to use both signals as well.
Thanks for your support.
>Just to clarify, when you say "first read" do you mean after initial power up?
Yes,"first read" meanes after initial power up.The data sheet of the ADS7807 does not mention that a dummy read is required after turning on the power supply, but it means that it is necessary?
Thank you for your answer.I will respond to customers.
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