PGA450Q1EVM: OTP programming and execution

Hi Arun,

The OTP programming procedure is explained in section 7.3.15.2.2 OTP Programming of the PGA450-Q1 datasheet. For an off-the-shelf mass production tool, I recommend the Acroview AP8000 for mass programming of the PGA450-Q1. Alternatively, the socketed portion of the EVM can be used, or you can develop your own SPI based PGA450-Q1 mass production tool.

The PGA450-Q1 offers 8kB of DEVRAM memory, which is reprogrammable volatile memory. By default, the EVM is programmed to operate in DEVRAM mode. The only problem with DEVRAM is that the OTP must be initially programmed to always run from DEVRAM, and from then on will always require the DEVRAM of the unit to be programmed on start-up / power-cycle. Once the OTP is programmed to jump to DEVRAM, the OTP cannot be reprogrammed again. This means that DEVRAM should be used for prototyping and development purposes. The process of configuring a device to run from DEVRAM is explained in section 11 of the PGA450-Q1 EVM User’s Guide. Once the code has been finalized and fully tested in DEVRAM, you should then OTP program production units for the code to run immediately upon startup.

To modify the source code made available through the PGA450Q1EVM firmware installer, download the Keil C51 Development Tool for all 8051 devices, which includes the uVision IDE necessary to open and edit the PGA450-Q1 project file. The PGA450-Q1 does not include an internal debugger, so an external debugging interface is required for breakpoint debug. Refer to the following source code for both DEVRAM and OTP versions of code: TIDA-00151 UART & LIN Demo Firmware for PGA450-Q1 ( www.ti.com/.../tidcab3 )

Hi Arun,

1. You can continue using your COM port on a PGA450-Q1 bus topology to test multiple devices. Assuming all device use the TIDA-00151 UART & LIN Demo Firmware, you only need to assign each of the four sensors with a different EEPROM value in EEPROM address 0x1F (I recommend values 0x01, 0x02, 0x03, and 0x04). This address value is used to differentiate which device the master should exclusively read/write.
For example, on your COM terminal, when you send a command to read back the time-of-flight data for device 3 out of the 4, the master would need to send: {0x00, 0x55, 0x23, 0x00} ({break field, sync field, command 2 at address 3, void checksum}). All other devices on the bus would ignore this command because only device #3 has it's EEPROM address 0x1F programmed with a value of 0x03.

2. Yes, you can DEVRAM or OTP program multiple devices on a SPI bus sharing the same chip select pin through the GUI. However, when using the GUI to program multiple devices, uncheck the "Verify DEVRAM/OTP Programming" check box. Only one device can be verified at a time since this is a SPI read command.