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Original question:

ADS127* output Settling time

ADS127L01: How to control the ADC?

Hongseok Oh
Prodigy 70 points
Part Number: ADS127L01

I'm trying to setup and use the ADS127L01 with Raspberry pi 3 model B, but it seems that I'm doing something wrong. I have two questions.

1. I have tied the CLK and SCLK and connected it to the SPI0_SCLK of RPi. Can this make any problem?

2. Previously when I use just simple 12-bit ADC, all that I did was lower CS, read the data, and raise CS. Here it seems that little more complicated. Is there any place that I can find some test source code for ADS127L01?

  • 0
    TI__Mastermind 47595 points
    Hello Hongseok,

    Thanks for your post and welcome to the forums!

    1) I can't find a reason that this wouldn't work, but typically SCLK is a factor of 2/4/8 times slower than CLK. What frequency are you operating the device at?
    From the datasheet "Drive the ADS127L01 with an external clock by applying the clock input to the CLK pin. At the maximum data rate, the clock input is 16.384 MHz for HR mode, 8.192 MHz for LP mode, and 4.096 MHz for VLP mode."
    2) Unfortunately we do not have any sample code available for the ADS127L01.

    I would suggest verifying that all supplies and clock signals are present as expected. As long as you are sending the master clock (CLK) and START is pulled high, you should notice that the /DRDY pin is toggling at the output data rate. This indicates that the ADC is converting and outputting new data. Have you verified this yet?
  • 0 in reply to Alexander Smith
    Prodigy 70 points

    Dear Alexander,

    Thank you for your advice! Following your suggestion, I have changed the configuration and checked the /DRDY, with CLK provided and START pulled high. I found that /DRDY pulses using an oscilloscope. It seems that the ADC is working (not damaged). However, I still get constant numbers from the ADC. I'm using SPI mode to communicate.

    When I write (0,0,0,0), the return is (0,0,0,0)

    When I write (18,0,0,0), the return is always (0,127,128,0), no matter which voltage is provided to the AINP of the ADC. (AINN is grounded).

    (18 = 0001 0010, a command to read the most recent data.)

    During the experiment START was pulled high, CS was pulled low, CLK = 10 MHz and SCLK = 100 kHz.

    I will check if all the connections to the ADC are right. Anyway, thank you for your help.

  • 0 in reply to Hongseok Oh
    Prodigy 70 points

    Oh, the REFN was floating for some reason. Now I fixed it and it seems working better.

    Depending on the voltage provided to AINP, I'm getting the MSB changed. However, only the first byte is changing, while the second and LSB keeps same (128 and 0). What should I do for this?

    For example, during the 4-byte SPI communication:

    Write buffer / Read buffer

    (18,0,0,0) -> (N, 128, 0, 0) (N varies depending on the AINP value.)

  • 0 in reply to Hongseok Oh
    TI__Mastermind 47595 points
    Hello Hongseok,

    I'm glad to hear that the device is still functional!

    Have you seen section 9.4,the initialization setup on page 77? It sounds to me like the ADC is not processing the inputs and is stuck.

    What registers are you writing to the device?
  • 0 in reply to Alexander Smith
    Prodigy 70 points
    Hi Alex,

    Thank you for your reply! I did not write anything to the register. I will check the section 9.4 and try initializing the registers.

    Sincerely,
    Hongseok.
  • 0 in reply to Hongseok Oh
    TI__Mastermind 47595 points

    Hello Hongseok,

    Additionally, can you provide some information on the input signals that you were applying from the previous post?

  • 0 in reply to Alexander Smith
    Prodigy 70 points

    Hi Alex,

    For the input signal, I hooked up a output of 10-bit DAC to the AINP of the ADC with a series resistor. 

    By the way, I have checked the register, tried some more measurement and got some progress.

    1. I checked the register and found that all the values are set as default. This was done by write (0010 0000) , (0000 0111) (Read register 8 bytes) and subsequently reading 8 bytes. So at least the ADC is well reading and send back its register value without malfunctioning.

    2. Then, I tried to read the different voltage (AINP) values. Strangely, sometimes it works fine but sometimes it doesn't. For example,

    when good

    Output: 81, 126, 023, XXX(CRC) (The number changes little but does not change much, maybe due to fluctuation & noise of the input)

    When bad

    Output: 81, 255, 249, XXX(CRC) (2nd and 3rd bytes are always same over repeated reading)

    Currently, I'm using the general purpose clock in the Raspberry Pi (GPIO #4). Can it make any problems?

    Thank you for following up this problem!

  • 0 in reply to Hongseok Oh
    TI__Mastermind 47595 points
    Hello Hongseok,

    I'm glad to hear that things are progressing.

    What is the frequency and magnitude of the signal that you're applying to the inputs when you see good and bad data?

    Unfortunately I cannot offer any support in regards to the Raspberry Pi. As long as the signal being input into the device is within spec it should be fine.
  • 0 in reply to Alexander Smith
    Prodigy 70 points

    Dear Alex,

    Currently the clock is having 3.3 V magnitude, 4 Mhz frequency.

    For the good and bad data, there is no difference in input signal. It is DC signal, and works fine at 1.0 V but bad at 1.1 V, and good again at 2.0 V. So I can't figure out what's wrong with it...

    Thanks,

    Hongseok.

  • 0 in reply to Hongseok Oh
    TI__Mastermind 47595 points
    Hello Hongseok,

    I'm sorry that we're having issues adressing this problem.

    Since the device seems to be operating normally and undamaged, perhaps this is an issue with other components in the system?

    Are you exceeding the limitations of the 10b output DAC or the amount of current that the RPi can handle?
  • 0 in reply to Alexander Smith
    Prodigy 70 points

    Hello Alex,

    Thanks for following up! I'm not sure which part is making problems. I will try another same ADC chip, and check if same things happen.

    Best,

    Hongseok.

  • 0 in reply to Hongseok Oh
    TI__Guru 57306 points
    Hello Hongseok,

    Since the data comes out correctly sometimes, and you are able to read the register contents, this sounds like an SPI timing issue during data collection. Are you monitoring /DRDY to detect the falling edge before you collect the data?

    Please capture the SPI signals during data collection (/CS, /DRDY, SCLK, DOUT) with an oscilloscope or logic analyzer. It is possible that a new sample is ready while you are reading old data. If that is the case, you will notice a /DRDY falling edge occur in the middle of your SPI transaction and the new data will overwrite the old data immediately.

    Best Regards,