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DAC39J84: 8B/10B disparity error in DAC39J84 setup?

Part Number: DAC39J84
Other Parts Discussed in Thread: LMK04828

I am seeing the SYNC signal go high, and it looks like the link is progressing past ILA to data, but I'm not seeing anything out of the DAC39J84 consistently. 

Here is a dump of the registers in the DAC (in decimal, high byte then low-bye format)

DAC Config Regs:
Config Reg 0
[0, 24]
Config Reg 1
[0, 80]
Config Reg 2
[32, 130]
Config Reg 3
[163, 1]
Config Reg 4
[0, 0]
Config Reg 5
[255, 3]
Config Reg 6
[255, 255]
Config Reg 7
[66, 4]
Config Reg 8
[0, 0]
Config Reg 9
[0, 0]
Config Reg 10
[0, 0]
Config Reg 11
[0, 0]
Config Reg 12
[4, 0]
Config Reg 13
[4, 0]
Config Reg 14
[4, 0]
Config Reg 15
[4, 0]
Config Reg 16
[0, 0]
Config Reg 17
[0, 0]
Config Reg 18
[0, 0]
Config Reg 19
[0, 0]
Config Reg 20
[0, 0]
Config Reg 21
[0, 0]
Config Reg 22
[0, 0]
Config Reg 23
[0, 0]
Config Reg 24
[0, 0]
Config Reg 25
[0, 0]
Config Reg 26
[0, 0]
Config Reg 27
[0, 0]
Config Reg 28
[0, 0]
Config Reg 29
[0, 0]
Config Reg 30
[68, 68]
Config Reg 31
[68, 64]
Config Reg 32
[64, 68]
Config Reg 33
[0, 0]
Config Reg 34
[27, 27]
Config Reg 35
[255, 255]
Config Reg 36
[0, 32]
Config Reg 37
[32, 0]
Config Reg 38
[0, 0]
Config Reg 39
[0, 0]
Config Reg 40
[0, 3]
Config Reg 41
[255, 255]
Config Reg 42
[0, 0]
Config Reg 43
[0, 0]
Config Reg 44
[0, 0]
Config Reg 45
[0, 0]
Config Reg 46
[255, 255]
Config Reg 47
[0, 4]
Config Reg 48
[0, 0]
Config Reg 49
[16, 1]
Config Reg 50
[0, 0]
Config Reg 51
[175, 64]
Config Reg 52
[0, 0]
Config Reg 53
[0, 0]
Config Reg 54
[0, 0]
Config Reg 55
[0, 0]
Config Reg 56
[0, 0]
Config Reg 57
[0, 0]
Config Reg 58
[0, 0]
Config Reg 59
[8, 0]
Config Reg 60
[2, 40]
Config Reg 61
[0, 136]
Config Reg 62
[1, 8]
Config Reg 63
[0, 0]
Config Reg 64
[0, 0]
Config Reg 65
[0, 1]
Config Reg 66
[0, 0]
Config Reg 67
[0, 0]
Config Reg 68
[0, 0]
Config Reg 69
[0, 0]
Config Reg 70
[0, 68]
Config Reg 71
[25, 10]
Config Reg 72
[49, 195]
Config Reg 73
[0, 0]
Config Reg 74
[255, 1]
Config Reg 75
[31, 0]
Config Reg 76
[31, 7]
Config Reg 77
[3, 0]
Config Reg 78
[15, 79]
Config Reg 79
[28, 193]
Config Reg 80
[0, 0]
Config Reg 81
[0, 255]
Config Reg 82
[0, 255]
Config Reg 83
[0, 0]
Config Reg 84
[0, 255]
Config Reg 85
[0, 255]
Config Reg 86
[0, 0]
Config Reg 87
[0, 255]
Config Reg 88
[0, 255]
Config Reg 89
[0, 0]
Config Reg 90
[0, 255]
Config Reg 91
[0, 255]
Config Reg 92
[17, 17]
Config Reg 93
[0, 0]
Config Reg 94
[0, 0]
Config Reg 95
[1, 35]
Config Reg 96
[69, 103]
Config Reg 97
[0, 1]
Config Reg 98
[0, 0]
Config Reg 99
[0, 0]
Config Reg 100
[9, 0]
Config Reg 101
[191, 15]
Config Reg 102
[223, 7]
Config Reg 103
[127, 15]
Config Reg 104
[255, 7]
Config Reg 105
[63, 15]
Config Reg 106
[127, 7]
Config Reg 107
[223, 15]
Config Reg 108
[0, 3]
Config Reg 109
[0, 0]
Config Reg 110
[0, 0]
Config Reg 111
[0, 0]
Config Reg 112
[0, 0]
Config Reg 113
[0, 0]
Config Reg 114
[0, 0]
Config Reg 115
[0, 0]
Config Reg 116
[0, 0]
Config Reg 117
[0, 0]
Config Reg 118
[0, 0]
Config Reg 119
[0, 0]
Config Reg 120
[0, 0]
Config Reg 121
[0, 0]
Config Reg 122
[0, 0]
Config Reg 123
[0, 0]
Config Reg 124
[0, 0]
Config Reg 125
[0, 0]
Config Reg 126
[0, 0]
Config Reg 127
[128, 10]

When looking for errors, I spotted the 8b/10b disparity error. I'm using an FMC120 from Abaco and a ZCU102, the FMC120/ZCU are both known to work (the Abaco demo runs). I'm now building out a system using the Xilinx core.

What could be causing this? Am I looking at the right spot? Does anyone familiar with this part see anything in this table of values that would go, "Yup, it's setting XYZ!"? 

Frustrated, but if it was simple it wouldn't be fun. Thanks all!

  • Hi Travis
    We have received your question. One of our DAC experts will provide a more detailed response to your question soon.
    Best regards,
    Jim B
  • Travis,

    Send me the LMFS settings you are using, along with the "K", and "RBD" values, the interpolation factor, SYSREF frequency, and DAC sampling frequency, and I will send you a working configuration file that you can compare to yours.

    Regards,

    Jim  

  • Hi Jim,

    L (#lanes) = 8
    M (#converters) = 4
    F (#octets per frame) = 1
    S (#samples per frame) = 1
    HD = 1
    RBD = 32
    K=32
    Interpolation = 0
    Sysref Frequency = 31.250MHz (The FMC120 has an LMK04828 on it, PLL2 is running at 3GHz and has a divide value of 96, so 31.250MHz).

    If you've got a config file that would work for this, I'd appreciate it.

    Here are the writes I'm doing to init the DAC - this is for the FMC120 on a ZCU102.

    // This resets the dac
    void reset_and_wake_dac()
    {
    u8 data;
    data = read_cpld(0x02);
    data &= 0xCF; // Reset and wake dac
    write_cpld(0x02,data);
    data |= 0x20; // Clear reset bit
    write_cpld(0x02,data);
    }


    void FMC120_dac_init()
    {
    reset_and_wake_dac();
    write_dac_spi(0x02, 0x0083);
    write_dac_spi( 0x4A, 0xFF1E);
    write_dac_spi( 0x46, 0x0044);
    write_dac_spi( 0x47, 0x190A);
    usleep(10000);
    write_dac_spi( 0x02, 0x2082);
    write_dac_spi( 0x01, 0x0050);
    write_dac_spi( 0x03, 0xA300);
    write_dac_spi( 0x04, 0x0000);
    write_dac_spi( 0x05, 0xFF03);
    write_dac_spi( 0x06, 0xFFFF);
    write_dac_spi( 0x1A, 0x0000);
    write_dac_spi( 0x1F, 0x4440);
    write_dac_spi( 0x1E, 0x4444);
    write_dac_spi( 0x20, 0x4044);
    write_dac_spi( 0x24, 0x0020);
    write_dac_spi( 0x33, 0xAF40);
    write_dac_spi( 0x3C, 0x0228);
    write_dac_spi( 0x3D, 0x0088);
    write_dac_spi( 0x3E, 0x0108);
    write_dac_spi( 0x3F, 0x0000);
    write_dac_spi( 0x00, 0x0018);
    write_dac_spi( 0x25, 0x2000);
    write_dac_spi( 0x31, 0x1000);
    write_dac_spi( 0x32, 0x0000);
    write_dac_spi( 0x3B, 0x0800); //config59
    write_dac_spi( 0x49, 0x0);
    write_dac_spi( 0x61, 0x01);
    write_dac_spi( 0x4B, 0x1F00);
    write_dac_spi( 0x4C, 0x1F07);
    write_dac_spi( 0x4D, 0x0300);
    write_dac_spi( 0x4E, 0x0F4F);
    write_dac_spi( 0x4F, 0x1cc1);
    write_dac_spi( 0x5C, 0x1111);
    write_dac_spi( 0x5F, 0x0123);
    write_dac_spi( 0x60, 0x4567);
    //
    write_lmk04828_spi( 0x10F, 0x11 ); Sets the output format of the device clocks. [Note that this is for the LMK, not the dac.]
    //
    usleep(50000) ;
    write_dac_spi( 0x4A, 0xFF1E);
    usleep(50000);
    write_dac_spi( 0x4A, 0xFF00);
    usleep(50000);
    write_dac_spi( 0x4A, 0xFF01);
    usleep(50000);
    write_dac_spi( 0x6C, 0x0);
    write_dac_spi( 0x6D, 0x0);
    for (u8 i = 0; i < 8; i++)
    {
    write_dac_spi( 0x64 + i, 0x0000); // Clear alarms
    }
    }
  • Hi Jim,
    Let me know if there's anything else you need - I could certainly use a second set of eyes, it's driving me crazy.
  • DAC39J84_841_1G_K32_1X_Int.cfgTravis,

    The attached config file uses your settings. With the FPGA configured on our setup, after applying power, I load this config file and get a valid output after it completes. Note that the command called "DAC_RESET" in the file is actually doing a hardware reset to the DAC. All other commands are register writes to the LMK and DAC.

    Regards,

    Jim

  • Jim!

    That helped a ton; here's what I'm seeing:

    On the FPGA side, I see that SYNC gets lost after data gets through, so we're passing ILA:

    Here's my question:
    Could the repeating SYSREF be to blame for the temporary loss of SYNC? 

    Seeing as how the SYNC gets (and stays) valid for such a long time before being lost only temporarily, that means it's probably not the frame buffer or a link issue - otherwise there'd be loss much sooner.

    Is there any other way I can attack this problem from the point of view of the DAC39J84? Or put another way: Is there a set of register reads I could do that would prove that the problem was on the FPGA side? 

    Thanks a ton, this has been a huge, massive help. It's SO CLOSE to behaving!

    EDIT: 

    I think sync_n is reporting an error:

    disable_err_report_link0/disable_err_report_link1 - config82 and config85, respectively?

  • Travis,

    Can you turn off SYSREF and see what happens? What if you divided SYSREF by 64 or higher? Does SYNC still change at every SYSREF edge or sooner? If this is an issue with SYSREF, there is a test you can do on the DAC side to verify the SYSREF is meeting setup and hold time. Follow the documents attached. Basically, if you run the DAC using the NCO output only, and synchronize the NCO logic with SYSREF, if you leave SYSREF running continuously, every rising edge of SYSREF will reset the NCO logic causing the frequency of the NCO to change. This will appear as many pulses on the DAC output when using a spectrum analyzer. If for some reason SYSREF was not captured properly by the DAC, the NCO would not reset and appear as one solid tone on the DAC output.

    On the FPGA side, are you providing the proper ref clk frequency? Is the RBD value less than K? Is matched on both ends?   

    Regards,

    Jim

    SYSREF trouble-shooting.docxDAC38J84 NCO SYSREF Test.pptx

  • I tried turning off SYSREF and moving to a pulse, triggered by SPI - no dice. I'm able to command a SYSREF pulse, but it doesn't solve the dropout issue.


    SYSREF is currently divided by 96 in the LMK04828 (register 0x13A/0x13B, SYSREF_DIV).

    The REFCLK for the FPGA should be 500MHz - that looks correct (also it has to be - otherwise I'd never see 0xBCBC for ILA).
    The core clock is 250MHz (line rate of 10Gbps/40 for Xilinx JESD core).

    SYNC is an input to the FPGA - transceivers being point-to-point links without the ability to apply backpressure, I don't think the FPGA can causing the issue. 

    It looks like the I'm seeing the error counter for link0 as all 1's (that's...a lot of errors). I'm in LMF = 841, so I'm thinking I'm only utilizing link0 (1 link containing all 4 converters).

    I tried changing the K value to 20 (down from 32) - I don't see a direct match for RBD in the Xilinx JESD core (instead it is listed as the size of a buffer, maximum octets per multiframe is 1024 - 20 frames, 8 lanes per cycle (so 8 octets), the buffer should be good enough (unless my math is off).

    I haven't tried the NCO debug approach to check sysref timing yet; I'll get to it this week and update this! Thanks for your help so far.

    After the updated config load, I see my ramp signal great on DAC A, but it looks "fuzzy" - it drops to 0 for the briefest instants. I'll update with pictures tomorrow!

  • Hey Travis,

    Jim is taking a look at your latest post and will get back to you ASAP.

    Thanks

    Yusuf
  • Travis,

    Anything new to report on your issue?

    Regards,

    Jim 

  • This is currently what I'm seeing on the output of the DACs; I'm expecing the ramp, but the fuzz I am not.

    This is what I'm seeing looking at the Sync line of the FPGA:

    Zooming out, you can see this pattern is repeated:

    Same behaviour when I pulse SYSREF rather than have it continuously running.

  • This is what I'm seeing at the output of the DAC. The ramp is expected - the fuzz is not.

    On the FPGA side:

    Zoomed out:

    You can see it is periodic, it drops out at the same spot every time, and it just isn't behaving. I'm pretty damn sure it has to be a setting, I just for the life of me have not stumbled on it yet. 

    I've set SYSREF to be a single pulse as well with no joy. It doesn't look like an EMI/C problem - too periodic. I'm looking at transceiver settings for the DAC - that makes the SYNC behave less predictably (so far), but seeing the results change is somewhat encouraging. 

  • I'm having this same issue with a Xilinx IP core and the dac39j84.  Looking for some additional TI feedback on this.

    David

  • David,

    What Xilinx FPGA are you using? If this is a custom board, please try the attached SYSREF test to verify you have the correct setup and hold time for this input.

    What is your sample rate, SYSREF frequency, lane mapping between the FPGA and DAC (If a custom board), LMFS settings, K and RBD values, interpolation factor, NCO settings (if used), internal PLL settings (if used)? With this information I can provide you with a DAC register configuration file.

    Regards,

    Jim

    3060.SYSREF trouble-shooting.docx