Multiplicative noise in DAC5681 output

I am using ADS5681 in a system in which it acts as an Arbitrary Waveform Generator (AWG) with a sampling clock frequency of 312.5 MHz.

When characterizing it with sine signals, I have found that the desired sinusoid seems to be modulated by low frequency random noise and various tones. There is nod additive noise but multiplicative. I came to this conclusion when programming the DAC with a constant digital signal, thus making the potential clock jitter irrelevant. The interfering signals where also present.

Then, I configured register BiasLPG_A (CONFIG6) to 0, thus programming a 95 kHz low pass filter in the DAC current source (instead of default value of 472 kHz). Then, the most offending spurs at +-610 kHz at -56 dBc vanished. Other reduced their amplitude.

However, some other remain, and most offending one is at +-4.8 MHz. I have made the following findings about it:

  • Spur level is proportional to carrier frequency (see figure below)
  • When changing the Full Scale current (by programming CONFIG7 register), the spur maintains relative level with desired signal
  • When reducing the sinusoid amplitude, the spur maintains relative level with desired signal
  • When changing the sampling frequency from actual 312.5 MHz to 250 MHz, the spur level reduces in an approximate ratio of 20*log10(Fs1/Fs2)
  • The spur is visible when configuring a DC signal, but level is low (as corresponds to low frequency tone)
  • The spur level changes level at DC depending on configured level: -80, -77 and -74 dBm when configuring maximum positive, zero and maximum negative value in the DAC.
  • When disconnecting the DAC active output driver and measuring with a transformer, the interference relative level does not change.
  • When bypassing RBIASJ, there are no observable changes.

There are other spurs at lower frequencies and with lower amplitudes.

In the board there are no switch mode power supply at this frequency. I have tested to change clock frequency of other digital elements in the board, without effect.

I have observed this behaviour in all the boards I have tested.

Do you have any clue on what may be happening?

Regards

Luis Miguel

  • Hi Luis,

    Sorry for the delayed response. Have you made any progress on this since your original post?

    If not, I'd like you to look at the power supplies on a scope to verify there are no oscillations. Are you using the EVM or your own board? Can you confirm that there are adequate bypass caps very close to each power supply pin?

    Thanks,

    Matt Guibord

  • In reply to Matt Guibord:

    Thank you Matt,

    Progress has been small but not null:

    • Power supply noise. There is a switch mode converter in the board, but operates at 500 kHz. These kind of noise is not so (spectrally) clean as the noise I measure.
    • I am using my own card, not EVM.
    • DAC bypass has been carefully placed and follows guidelines.
    • I think the noise is caused by the clock deterministic jitter, but I am not absolutelly sure, because if it where so, no noise could be measured at DC DAC output. The strongest fact for this hypotesis is linear dependence of spur level with DAC signal frequency.
    • Clock distribution: clock is generated by CDCE62005. Output Channel 0 goes to DAC and Channel 1 to an offboard FPGA (LVDS). The FPGA divides this clock frequency by two and sends it back to the DAC device (LVDS). I have measured this clock spectrum isolating with a transformer and I have been unable to measure noise at this frequency offset. This is data clock. The measurement of sampling clock (CLKIN) does not reveal noise at 4.8 MHz frequency offset.

    I am still working on it.

    Best regards

    Luis Miguel

  • In reply to Luis M Brugarolas:

    Luis,

    Can you send me your register settings? I'd like to set this up in the lab with our EVM with your configuration.

    It seems like some frequency might be coupling in from your board, but I'd like to see what my results look like.

    Regards,
    Matt Guibord

  • In reply to Matt Guibord:

    Dear Matt:

    Config data is as follows, and in described order. It is in [Address; Data] format

                  [   hex2dec('08') ; hex2dec('04')]
                  [   hex2dec('02') ; hex2dec('40')]  # Binary offset format
                  [   hex2dec('05') ; hex2dec('80')]  # 4 wires serial IF
                  [   hex2dec('0A') ; hex2dec('CE')]  # Fs is 300 to 350 MHz
                  [   hex2dec('08') ; hex2dec('00')]
                  [   hex2dec('07') ; hex2dec('FF')]  # Full DACA_gain (16)
                  [   hex2dec('06') ; hex2dec('04')]  # Filter of source bias 95 kHz

    Sampling frequency is 312.5 MHz.

    Best regards

    Luis Miguel

  • In reply to Luis M Brugarolas:

    Hi Luis,

    I set up the EVM in the lab with your register settings and I don't have any spurs close to my fundamental, including no spur at 4.8 MHz offset. This leads me to believe that the DAC is not at fault and instead the signal is coupling into the DAC from another source on your board. I have a couple of suggestions for you below.

    1. It is possible that an internal clock divider is leaking onto your clock line. What is your reference frequency and what are your PLL settings for the CDCE62005?

    2. It is possible that you have timing errors. Can you set your data lines to all 0's and turn on the fs/4 mixer? CONFIG1 = 0x10 and CONFIG2 = 0x41. This should generate a tone at fs/4. Do you still have the spurs?

    3. If you have a scope with infinite persistance, look at the data clock and see if the duty cycle of the clock varies from cycle to cycle.

    Lastly, can you provide screenshot of your measured spectrum around the fundamental?

    Regards,
    Matt Guibord

  • In reply to Matt Guibord:

    Hello Matt,

    Thank you for your interest, and sorry for the delay: I had urgent tasks. It is good news there are no spurs in EVM.

    1.- Clock divider. CDCE62005 uses a 25 MHz VCXO with control voltage set to mid supply. PLL comparison frequency is 6.25 MHz. The device configuration is as follows. Remember last nibble corresponds to address, and remaining 28 bits to data.

                    'eb800300' # DAC_SCLK:     LVDS, Internal VCO
                    'eb800301' # DAC_FPGA_CLK: LVDS, Internal VCO
                    '68860302' # Unused:       Disabled
                    '83400003' # ADC_SCLK:     LVPECL HS, PRI-IN: Frac-N reference
                    'eb800314' # Test port:    LVDS, Internal VCO
                    '100c0b25'
                    '04be09a6' # ENCAL_MODE = 1 && ENCAL = 0
                    'bd0037f7'
                    '80009DD8'

    2.- Your suggestion is very interesting, but I am unable to enter in this test mode besides my trials. As this mode is undocumented, I could not test if reported configuration is correct. Could you re check it?

    3.- Duty cycle variation in data clock (DCLK): I am able to measure a 220 ps peak to peak duty cycle variation. Actual jitter will be something lower due to scope (TDS 744A) trigger jitter. When measuting clock with the Spectrum Analyzer, I can measure -53 dBc at 60 MHz. No jitter can be measured at 4.8 MHz altough phase noise at this frequency is far from being negligible (see attached photo)

    4.- Spectrum plots: As I do not know what plot you are asking for, I will include both for clock and DAC output.

    DAC Data Clock Spectrum: Low quality but readable. Marker delta at 4.8 MHz. SPAN is 12 MHz and Central frequency 156 MHz

     

    DAC (plus driver) output spectrum when signal is Fs/4. Despite incorrect marker delta legend (I do not know why), the +-4.8 MHz spurs are clearly visible.

     

    Hope this helps

    Best regards

    Luis Miguel

  • In reply to Luis M Brugarolas:

    Dear Matt,

    Thinking twice the Data Clock jitter measurements, I have come to the conclusion that is reasonable to think taht this clock has no influence at all in output spurs, as this clock is just used to write data in the DAC internal FIFO.

    Best regards

    Luis Miguel

  • In reply to Luis M Brugarolas:

    Luis,

    The concern is that if there was too much jitter on the data clock you might violate setup and hold times. 220ps should be sufficient.

    Regarding number 2. We do not have a test mode for this, but you could configure your FPGA to output all 0's.

    I'll review the CDCE settings and get back to you.

    Regards,
    Matt Guibord

  • In reply to Matt Guibord:

    Luis,

    I had our clocking team look into your CDCE settings and they also did not see any spurs around 4.8 MHz. They did mention that the loop filter was set to a wide bandwidth and that you might be able to get better performance with a lower bandwidth filter.

    Regards,
    Matt Guibord

  • In reply to Matt Guibord:

    Could they suggest a register configuration? I worked with the excel datasheet but I could not reach to sucessful configuration.

    Best regards

    Luis Miguel