We use adc10d1500 as a data sampler front end. This adc is followed by a Atera's FPGA, ep3se110. We test the converted data of the ADC in the FPGA last night. It worked well. But this morning there were many glitches at each channel when we turned on the circuit for the first time. Then we turned off the circuit and turned on it again. The converted data functions in an abnormal state. Some lvds channels output a constant value, and some output random data. When this chip is set in Test Pattern Mode, the output data is the same as describled in the datasheet, which means the output logic still works well. How can I solve this problem?
Hi Rung,
It's interesting that the system worked last night, but was not working this morning. It sounds like a little more debug is in order. It's possible that there is a marginal timing issue, which means that the system does not always power up in the proper sequence. If the analog input was over-stressed, to the point that it was broken, I would not expect to see constant values at any particular data bit, so it's not likely that that has occured.
Here are a few modes to check:
1. Test Pattern Mode - it's good that you checked this already and verified that the issue is not taking place at the output.
2. Normal mode (non-Test Pattern Mode) with no signal at the analog input. For this setup, the output should be codes within several codes range of 2047/2048.
3. Normal mode (non-Test Pattern Mode) with a slightly over-range or under-range input. For this setup, the output should be all 1's or all 0's.
4. Normal mode (non-Test Pattern Mode) with a CW tone. Please post the FFT.
Are you operating the part in Extended Control Mode (ECM) or pin control mode (non-ECM)?
Please describe the initialization for the system, e.g. power on, application of sampling clock, programming the register in ECM, application of analog input, and any other relevant events.
What kind of analog input are you converting - and at what typical levels?
Kind regards,
Marjorie
Hi, Marjorie Thank you for your reply! The analog power supply and digitial power supply is fed by the same output of a single 1.9V power chip, lt4616, a switch power chip produced by linear techonoly. The two power is seperated by beads. There are two adc10d1500 in a board, one acts as master and another as slave. Both chips are configured in ECM mode. After power up, a FPGA behind configures the work mode, one as master and another as slave. We omitted the power up sequence due to the same power supply of the analog one and the digital one. The input signal is converted from a single ended signal to a differential one and then fed into the input + and input -. The SPI signals are fed by FPGA which corresponding bank is supplied with 1.8v supply. The input clock is a square wave signal which is AC coupled and the differential mode voltage is 450mV peak to peak.
The input signal is AC coupled to the adc. So constant value cannot be fed at the input. Wheter there is a slightly under-range CW signal or no signal at the analog input, the output of the signal is nearly a constant value.
Rung
Sorry for the delay in response - I hope you enjoyed a nice weekend.
Thanks for the additional info. It appears that the power supply and SPI interface are operating correctly, since you can program the part into Test Pattern Mode. Here are a few more points of diagnosis:
1. What is the maximum level of the analog input? Was the analog input ever applied to the ADC while it was powered down? Can you verify the input signal on a spectrum analyzer?
2. Try changing the value of the Full Scale Range or offset of the input - does the output change? I'm starting to wonder if the analog input did get fried. If so, the ADC may be converting the same value at its input - and the value at the output would only change for an adjustment to the offset or FSR.
Hi Marjorie,
Thank you!
The adc maybe got fried. I will check the output when adjusting the FSR and offset. The chip had ever been applied analog input when powered down. Is it the most likely reason which damaged the chip or something else? Is it necessary to add a protection circuit before the analog circuit?
Yes, it's a very good possibility that the ADC analog front-end got fried. No analog input should be applied when the chip is powered down. Please let me know the results of the experiments with FSR and the offset, when they are available.
The Absolute Maximum Ratings and Operating Ratings in the datasheet show the limits to the analog front end. When powered up, the current to the analog front-end should be less than +/-50mA. If the circuit which drives VIN+/- ever exceeds that, then a protection circuit should be included in the design.
Let me know if you have further questions.
Sorry to reply you too late! We tried to verify the problem of the analog input.
1. There was no effect on the device lvds output when changing the offset value.
2. The output value changed when changing the FSR value of I-channel. However, the value of Q-channel kept the same while changing FSR. In the I-channel, the lower 20-bits changed its value according FSR. The higher 20-bits output many glitches.
3. By comparing the electric charactoristic of a new chip and a damaged one, we cannot find any differences between them. It seems that the damaged chip is the same with a new one.
Hello Rung
Regarding your latest response and findings.
Since the FSR setting did change the output somewhat, but only on one channel, it sounds like the issue could be damaged input circuitry in the ADC. Just to confirm, does putting the part into Test Pattern Mode still provide the correct output data as captured by the FPGA?
When you say you are comparing the electrical characteristics between a new chip and the possibly damaged one, what things are you measuring?
Would it be possible to provide a schematic of the ADC portions of your system? I would like to do a quick review of that circuitry just to make sure everything is OK.
Best regards,
Jim
Hi Runglee,
I got struck with the same problem TPM mode ADC showing correct results but when i fed input it is not responding. Have you got any solution for the problem? Plz let me know if you have any suggestions.
Hi Krishna,
Can you confirm whether you are using one of TI's reference boards - or your own design?
If the output is function, that is a good sign. It's just the input which must be debugged. Here are a few things to check:
1. Look at the signal source on a spectrum analyzer or scope to confirm it is operating as expected.
2. View the output of the ADC with no input. It should show just a little noise with perhaps 10 LSB variation. Can you confirm this?
Hi,
Thanks for the reply.
This is my own design but taken from the reference board (AD12D1500 - Virtex4 board). I can share you some observations which i observed
on chipscope pro.
When I fed the same data input to the Reference board I have I could able to get the data without any problem(Virtex 4-ADC12D1500 Board).
Please help so that I can do my things at faster rate.
Attaching the TPM mode data Captured in Chipscope Pro:
Thanks again.
Krishna Gadde
Hi Krishna
Please provide a longer duration chipscope capture with the ADC in TPM. I'm not sure from what you've shown that captures are working 100%. The pattern should repeat every 5 symbols on each lane, as shown below. Note that the first and 5th symbol in each block are the same, so you should get 2 symbols in a row that are the same.
Are you using the same hardware design as the TI reference board? Did you start with the provided source code for the Virtex 4 FPGA? I want to understand what items are the same as our reference board, and what have been changed to help pin down what the problem might be.
I hope this is helpful.
Jim B
Hi Jim,
Hardware Differences:
Evaluation Board Our Board
AD12D1500 AD10D1500
Balun is used on Board Transformers ( we require AC coupled Input only)
Virtex4 Virtex 6 (475T)
thats it and I am not sure of two pins in the reference design and my design POREN, WSS can you plz suggest the potential they need to be with ( they are now open).
One more thing Intially i have used Pin control mode and now I am using SPI Mode through which I could able to do all the things (Power down, Mode configurations etc.,) Still I will check others Plz suggest me if anything is required as a prerequisite for Inputs especially.
Thanks again,
Refer to the product datasheet for the specific pins designated as POREN and WSS in the reference design schematics. Our first guidance is always to follow what is shown in the product datasheet. If you do that everything will work correctly.
If your system is configured for AC coupling, there should be capacitors between the outputs of the balun and the inputs to the ADC and the Vcmo pin should be connected to ground directly, or through a low value resistor (<100 ohms). If this is done, then with the input to the balun terminated you should see the ADC outputs at very close to mid-scale. If the data captured is not consistent, or is any significant amount higher or lower than mid-scale I expect you are having data capture issues. In that case, please take a look at a longer capture with TPM = 1. (7 samples or longer to be able to see the 5 sample repeating pattern).
I agree with Jim's response. In addition, you may also check AN-2128 for a more detailed explanation regarding those pin names:
http://www.ti.com/lit/an/snaa072b/snaa072b.pdf
Thanks for your answers,
Now I could able to read the data after configuring with SPI but I really want to know the reason why it has not happening with PIN CONTROL MODE.
Anyways I will follow the application note AN-2128 which is really useful for me, while designing i followed datasheet whenever there is a connection to a potential as per reference schematics i made a provision of 0E so I could make DNC of those thing which I have done now.
Thanks for your support.