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hello,everyone,
I am trying to do some evaluation on ads62p29 EVM_rev_C board.
This is what I got from the DDR LVDS interface.RX_OUT_oddl[11:0] is the signals from the ADC's LVDS after the DDR_LVDS logic in the FPGA board.
I don't have the TSW1200, so I evaluate the ADC in my Altera ArriaII board.
All the configuration is default.
CLK of the ADC is a external 150MHz. （use option3. LVCPEL without 245.76MHz filter）
Input signal is a sine wave (Vpp = 1V, frequency = 200KHz, Voffset = V, 50om resistence signal output from a Function waveform generator)
More over, either the sine wave or square wave input ,the output is no different. All these output seems like a square wave(very likely the picture blow)
if I change the signal's input frequency or amplitude , the waveform changes as it should be. (SO the signal has been transmitted to the FPGA)
What's more, I change the SEN from LVDS 2's complement to LVDS binary offset. There is no difference between what I got from FPGA.
Can anyone help me to explain this ?
thank you
Alan
Hi Alan,
First, I think you need to verify that you are recieving the data correctly from the ADC. The ADS62P29 provides test modes to verify the correct transmission of data. You can use the "TI ADC SPI Interface" software tool to put it in this test mode. One of the most useful patterns is to provide a custom pattern where you set only one bit at a time and verify that that bit is being read and placed correctly. Do this for all bits. Once bit placement has been verified, you can use the toggle pattern and digital ramp to verify correct timing.
http://www.ti.com/tool/hsadc-spi-utility
Regards,Matt Guibord
hi,matt,
thank you very much for your reply.
I've tried this spi_gui to verify my EVM. Here is some screen shot from oscilloscope under test pattern.
pic1 is LVDS_CLK pair waveform.
pic2 is data pair waveform under toggle mode.
pic3 is ramp pair wave form under ramp mode.
all waveform tested in the configuration: LVDS output ,low speed, 2's complement.
As you can see . It seems that lvds clk is abnormal.
Then I tested this under the CMOS output : clk output is as follows.
The input clk is from a sigal generator and is a 20MHz, 1.5Vpp, sine-wave signal as the user's guide said.
I am depressed for this strange thing.
I am very appreciated for your letter.
thx.
Alan,
Have you enabled low-speed mode? Do this by writing 0x04 to register 0x20. This mode should be enabled for clock speeds slower than 80 MSPS.
Secondly, the DLL in the part is incapable of keeping a 50% duty cycle for such slow clocks. The duty cycle distortion is expected, however setup and hold times should still remain sufficient and should not effect performance.
hi,Matt,
thank you for your quick reply.
As I mentioned that all waveform tested under the configuration: LVDS output ,low speed, 2's complement which was set by ADC GUI instead of the low-speed register.
I am confused about the DLL module. Do you mean 20MHz is beyond its lock capability？
Then I will have a try with a high speed external clk (>80MHz).
best regards.
As you decrease the sampling frequency the timing only gets better and therefore the DLL is no longer needed to guarantee correct timing. Thus we use low speed mode to disable it.
Hi,Matt,
Thank you for your reply.
I have another question about the CLK input of high speed ADC.
As I known, high performance sample needs clean and lower jitter CLK input. If the on board crystal is used, the low pass filter and PLL is needed for the VCXO crystal.
Compared with crystal solution, DDS maybe is another choice for good CLK source.
I want to use high speed ADC for ADS62P29 external clk. I checked the AD9854 and AD9910(both manufactured by ADI company ) can support high speed sine-wave output, the maximum frequency of AD9854 is 120MHz and later is 400MHz.
Is that realistic for ADS62P29 EVM's CLK source or is there any risk I have to take into account?
Regards,
ps:AD9854 specification
http://www.analog.com/en/rfif-components/direct-digital-synthesis-dds/ad9854/products/product.html
I have got the expected result after a 120MHz clk source is used to drive the ADC.
But you still have not answer my question about ADC CLK.
Thank you very much.
here is my last letter.
I do not think that is a good choice for this. The RMS jitter in clock generation mode is 25 ps. We generally recommend less than 1 ps of jitter. A better choice would be the LMK03806 or LMK04800 using a good quality cyrstal or VCXO. Take a look at these.
http://www.ti.com/product/lmk03806http://www.ti.com/product/lmk04800
Matt,
Thank you for your suggestion.
I am a freshman in this field.
Your help is greatly appreciated.