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     The ADS4249 datasheet, September 2011 revision, is missing some timing
information related to the control bus interface.
     List item 4 on page 21 explicitly says that the user is expected to use
the falling edge of SCLK to sample SDOUT, which is also implied by Figure 11.
Given that this is an SPI-like interface and the names are SPI-like, plus
Figure 11's implication, it appears that the rising edge of SCLK is when the
ADC puts out SDOUT, but this is never said, as timing information for SDOUT
are also missing.  Two questions:
 
1)  What edge of SCLK changes SDOUT?
2)  What are the timing characteristics of SCLK to SDOUT (t(CO))?
(They are not in Table 9 on p. 19 where timing is described, nor did I find
them anywhere else.)

     Additionally, since this is an SPI-like interface, I wanted to confirm
what the DS says about the distinctly non-SPI behavior of SDOUT.  On page 21,
SDOUT is described as being high-impedance when the internal READOUT control
is 0, and driven when READOUT is 1.  No mention is made in the text of SDOUT
being driven or Z with respect to SEN, although the timing diagrams show
that SEN is unrelated to the SDOUT state.  Since this is such a strange
design, I'd like to confirm this is true:
 
3)  Does SEN really not have the ability to tri-state SDOUT?  That is,
is SDOUT Z versus driven solely controlled by the READOUT control bit?
                                
     Lastly, the datasheet never says what the bit order of the data outputs is,that is, the DA and DB pins.
4)  Which D[AB] bit is most significant, 0 or 13?

     Thank you,

Craig