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ADS4249 serial interface and bit-order questions
The ADS4249 datasheet, September 2011 revision, is missing some timinginformation related to the control bus interface. List item 4 on page 21 explicitly says that the user is expected to usethe falling edge of SCLK to sample SDOUT, which is also implied by Figure 11.Given that this is an SPI-like interface and the names are SPI-like, plusFigure 11's implication, it appears that the rising edge of SCLK is when theADC puts out SDOUT, but this is never said, as timing information for SDOUTare also missing. Two questions: 1) What edge of SCLK changes SDOUT?2) What are the timing characteristics of SCLK to SDOUT (t(CO))?(They are not in Table 9 on p. 19 where timing is described, nor did I findthem anywhere else.) Additionally, since this is an SPI-like interface, I wanted to confirmwhat the DS says about the distinctly non-SPI behavior of SDOUT. On page 21,SDOUT is described as being high-impedance when the internal READOUT controlis 0, and driven when READOUT is 1. No mention is made in the text of SDOUTbeing driven or Z with respect to SEN, although the timing diagrams showthat SEN is unrelated to the SDOUT state. Since this is such a strangedesign, I'd like to confirm this is true: 3) Does SEN really not have the ability to tri-state SDOUT? That is,is SDOUT Z versus driven solely controlled by the READOUT control bit? Lastly, the datasheet never says what the bit order of the data outputs is,that is, the DA and DB pins.4) Which D[AB] bit is most significant, 0 or 13?
1. I'd suspect that the rising edge changes SDOUT and thus the falling edge should be used to sample it. See figure 11 in the datasheet. I'll clarify this with the design team.2. I'll have to check with the design team.3. Correct, SEN does not control SDOUT. The state of SDOUT is controlled solely by the READOUT control bit.4. All of our high speed data converters follow the MSB to LSB format of highest number to lowest number. That is bit 13 is the MSB and bit 0 is the LSB.
Thank you for the first few answers. I'll look forward to getting the timing information.
Here are some more information about your question. What is your SCLK speed?
A3: Relationship between SDOUT and SEN should be same as between SEN and SDATA. Yes, only readout register setting is enough to put device in readout mode. Note that register 0 can't be read back as it contains reset and readout bits.
A4: Bit0 of output data of channel A or channel B should be sampled at rising edge of output clock. Bit1 at falling edge.
Hi,SDOUT is placed at rising edge of SCLK by device, so that external receiver can latch it on falling edge of SCLK.SDOUT seems to have about same setup and hold time numbers all through the SCLK frequency of operation.Below is the SDOUT timing experiment results sheet (on Room Temperature and Nominal Supply Voltages).
Thank you for the timing numbers. It appears that the clock-to-data-out time (t(CO)) is in the range of 3.2-4.8 ns, which gives something reasonable to work with.
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