From the absolute maximum rating (datasheet) for the Analog input positive to Analog Input Negative (continuous AC signal) of the ADC is given to be 1.25V to 3.75V. Why is this value given as a range? Why is it not one value?
Can you please let me know ASAP,
I have spoken with the author of the datasheet, and I suspect that there was an editing error in the creation or maintenance of the document somewhere. I will be working to determine exactly what belongs in this field of the datasheet. We have just gotten from the designer the max current density limits for these structures for a similar device so that we could update this same specification for that device, so I will try to do the same for this device as well.
thanks for the prompt response.
In the meantime can i get a "number" the absolut max value?
This is due to the internal biasing of the input. Please note this is centered about 2.5v.
See equivalent input circuit:
I got clarification from the designer as to what we are trying to say in the absolute max table.
For the analog inputs, Wade Vonbergen pointed out that the desired common mode of the differential inputs is 2.5V and the numbers in the table range symmetrically about 2.5V. Yet the definition of the spec is the voltage between the pins, rather than to ground. The designer confirms that he was thinking of these input voltages as relative to ground rather than differentially, so we do need to fix the datasheet to clarify what we mean.
Let me start with normal full scale input of 2V peak to peak. With a common mode voltage of 2.5V, that would mean that AINP and AINN would each range about 2.5V by as much as 0.5V, so each input pin would always be between 2.0V and 3.0V. And the signal on these two pins are expected to be symmetrical about 2.5V, such that at all times the common mode of the signal would be 2.5V. For example, while AINP might be at 2.75V then AINN should be at 2.25V, and this example would be halfway to positive full scale. This is our recommended operating spec - to stay within full scale of 2V peak to peak centered around common mode.
If the input signal is larger than full scale, that is ok. The ADC will just clip the signal at full scale and output the max or min sample codes of 0000 0000 0000 or 1111 1111 1111. But if the input signal is a *continuous* AC signal that is larger than full scale then the max that we want to see is +/- 1.25V about common mode, or 5V peak to peak. That is, we could have a continuous sine wave of amplitude 5V peak to peak at the ADC inputs forever without damage. This corresponds to each side of the diff input swinging between 1.25V to 3.75V, which is 1.25V above or below common mode. We could tolerate this forever before we would worry about metal migration. So this is where the numbers for continuous AC signal come from.
But if the input signal is *not* an AC signal but rather a constant voltage, then we have to back off this a bit. The max *continuous* DC input would be limited to a range of 0.75V above or below common mode, but still with common mode at 2.5V. This would correspond to 3V peak to peak signal range, but since we are talking about DC and not an AC signal, this is where the dsigner switched from thinking in terms of peak to peak and rather went to pin to ground. Again the limiting factor is metal migration, and the AC signal cane be larger than this because it *is* AC and is not at its max or min point all the time. The DC spec is for a signal that *is* at this value all the time. So this is where the numbers 2.75V to 3.25V for DC continuous signal come from.
The short-duration spec is for things like glitches or ESD events. This is a fusing limit. The signal on each pin should remain in the range of -0.3V to 5.3V in order for the ESD diodes to not turn on and begin to draw current. Even then this event is ok *if* the source is current limited. For example, we routinely violate this in the lab when we have the signal generator turned on with the bench power supply off. A sine wave from a 50 ohm source is inherently current limited and can’t source enough current to pop the ESD structure.) Short term to the designer is a duration of microseconds to a millisecond or two.
But if you have a short-term signal during power up that is larger than full range signal but within the supply range then it does not fall into any of these categories. It would not be large enough to turn on the ESD diodes, I believe, so then that spec doesn’t apply. It is not a *continuous* event, so neither the continuous AC signal nor continuous DC signal specs apply. In other words, the designer sees no problem with a signal from an amp at power up that might go well above full scale for a duration of some milliseconds. It is not continuous. And it will likely not go above or below the supply/ground of the amp sourcing the signal. So it would not violate any of these specs. If this event happened so often and for so long that it began to look like a 'continuous' input, then metal migration would begin to be the issue and the 'continuous' max specs should be considered.
We will try to clean up the wording in the datasheet, and I hope also I can get a current limit number from the designer to elaborate further on when it is ok to violate the -0.3V to 5.3V spec when the source is current limited. I have asked for this last piece of information because that question also arises from time to time.
i hope this clears up what we meant and what we spec for this input.
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