I am using a TSW3100 together with a DAC5682z.
Having some trouble figuring out why the change in interpolation and Y2 divider alters my output spectrum so much, which you can see in the pictures below. Can someone first explain what the Y2 and Y4 dividers do?
The signal is a basic two tone (1 MHz).
With 2 times interpolation and Y2 set to 8:
With 4 times interpolation and Y2 set to 16:
In the picture above I forgot to change the frequency for the two tone and thus it is half compared to the first picture.
Thanks in advance!
Y4 is the divider for the DACCLK. If your DAC output sample rate is 1 GHz, then the clock fed to the clocking input should be 1 GHz and a divide by 2 setting should be used. Generally, just keep it at divide by 1 and apply your final DACCLK rate to the clocking input.
Y2 is fed back to the FPGA on the TSW3100 to control the rate that the pattern is pulled out of the DDR memory on board. The correct rate is calculated by the equation below. For an interpolation of 2 and using dual DAC mode, the correct divider ratio is 8 since NUMDACS cancels with Interpolation. For the 4x case, NUMDACs is still 2, but Interpolation is 4, so the correct divider is now 16. It seems you've figured this out and it looks like you have it setup correctly.
Ffpga = (DACCLK*NUMDACS)/(8*Interpolation)
We'll often need to resync the device after changing any of the clocking or digital settings. Can you try setting your "sync source" to "soft sync" so it can be controlled through software and then toggle the "software sync" button. This may fix your problem.
I notice from your screen shots that you're not using the DLL. Is this because your sample rate is low? What is the DACCLK frequency that you're using?
Thanks for your reply and explanation! I'm starting to get a picture how this card works now.
How do I control the sync from for example Matlab? I am not using the provided TI programs since I want everything in matlab.
I bypassed the DLL since my sample frequency is 20 MHz. It should be bypassed if you have a sample rate below 150 MHz, right?
Below are some pictures with and without software sync. There is a strong carrier leakage, fc = 1 GHz undersampled to 40 MHz.
Without soft sync and no signal
Two tone 2x interp, without soft sync
Two tone, 4x interp, without soft sync
With soft sync
Two tone, 2x interp, with soft sync
Two tone, 4x interp, with soft sync
When using the SW_sync option, make sure to set SW_sync_sel to 1 as well.
Since your sample rate is so low (20 MHz), I'm not sure the TSW3100 will work. The lower limit for the TSW3100 clock is about 20 MHz. This is limited by the RAM interface. If using LVDS (such as with the DAC5682z), then the lower limit for LVDS sample rate is 20 MHz * 8 samples = 160 MSPS.
Thanks for your reply.
I think the problem is solved now. It got perfect results when using a sample rate of >50 MHz. The 4x interpolation works now and the evaluation board is much more stable.
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