I have the ADS6129 coupled to TSW1200 evaluation board. I need to synchronize the ADC acquisition to an external trigger via the FPGA and send the data using a USB 2 or 3 (I already have the small USB card). I would like to have access to the VHDL code to simply add the trigger and modify the Data Output format without changing the internal FPGA code. Could you please provide me the appropriate code files?
The TSW1200 already supports an external trigger option that sounds like what i think you are asking for.
In recent versions of the TSW1200 GUI (version 2.5 is the most recent version on the TI web) you should see a checkbox labeled as External Trigger that is next to the Capture button. If you check this checkbox and then press the Capture button, then the TSW1200 hardware becomes 'armed' for a capture but the capture cannot begin until an external trigger is seen at the FPGA. We wired that external trigger signal to the pushbutton switch SW4 on the TSW1200. A rising edge on the external trigger is the external event that causes the data capture to begin.
You can test this functionality by setting up the ADS6129 EVM with the TSW1200 and verifying that the capture button works. Then if you check the External Trigger checkbox and press Capture, you see the GUI goes into a wai state with the Capture button now saying Capturing. If there is not an external trigger in abotu 15 seconds then the capture times out. While the GUI is waiting fr the capture to complete, reach over and press SW4. You should see the capture complete right then and the captured data is then processed.
If this is the type of trigger functionality that you are looking for, then you would want to connect *your* trigger signal (we look for rising edge of the trigger signal) to one side of SW4.
If this is not what you are looking for, then we do supply the Verilog source code of the TSW1200 upon request if you supply an email address for us to send it to. Usually we get requests for the Verilog source code from people who wish to copy the ADC interface code for their design. The source code we provide includes the constraint file for the pin assignment on the TSW1200, but we would not be able to guarantee you would be able to recompile and get a new bit file that worked seamlessly with the USB interface from the PC. That PC interface into the FPGA to control capture operation of the TSW1200 was not documented for public support.
thank you for your reply. It is very good news to know the trigger input is already there, I'll try it right away. What I forgot to mention in my post was the presence of a motor encoder output to be packed together with the AD output and then sent out through the USB port. The encoder output will be clocing an internal counter whose digital output will be merged with the AD output, this is my basic idea. If you can please send me the Verilog code to: email@example.com I will appreciate it. It will give me for sure a better global view of the whole acquisition system.
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