Forums

LM98640QML miscellaneous questions

This question is answered

Posted by Kazuhiko Hirano

on May 16 2012 19:58 PM

Intellectual2350 points

Hello,

My customer has some questions about LM98640QML-SP as follows.

Please respond to their questions.

Q1:

The datasheet says tLAT = 10 x TADC(max).

The TADC is 1/fINCLK?

Q2:

Nth sampled data gets available after tLAT + tDOD from INCLK rising edge?

Q3:

Is the tLAT always 10 x TADC(max)?

If not, what are the tLAT(min) and (typ) respectively?

Q4:

How much could the skew be among TXOUT0, TXOUT1, TXOUT2 and TXOUT3 over PVT?

Q5:

In CDS mode, which data comes out first, Odd output or Even output?

Are their any ways to define which comes out first?

Or, which comes out is not deterministic and monitoring TXFRM is the only way to know which it is?

Q6:

At the INCLK Range Register, bits[1:0](DLL Range) are set depending on bits[6:4](INCLK Range) setting as follows?

[6:4] [1:0]

000 10

001 10

010 01

011 01

100 00

101 00

Q7:

On the AFEval GUI, users can set bits[6:4](INCLK Range) of the INCLK Range Register.

However, regarding bits[1:0](DLL Range) of the INCLK Range Register, there are only two choices, "Normal" and "Reset".

What are bits[1:0](DLL Range) set for "Normal" and "Reset" respectively?

Q8:

The datasheet states "VDD18 Input Pin" in the absolute maximum rating section.

Which pins are exactly categorized into "VDD18 Input Pin"?

Please tell all "VDD18 Input Pin"s at LM98640QML-SP.

Q9:

Regarding VDD33 and VDD18, are there any power up sequence users have to follow?

Q10:

When either VDD18 or VDD33 is ON and the other is OFF for long time, could LM98640QML-SP get damaged?

Q11:

The user measured fSCLK on the LM98640CVAL Evaluation Board.

It was around 40KHz and much lower than the 1MHz specified as minimum in the datasheet.

Why?

Q12:

At customer's application, they use 10MHz for INCLK.

In this case, the device internal system clock frequency would be 640MHz (10MHz x 64)?

Is this the maximum frequency in the device, or the DLL could internally generate higher frequency than 640MHz?

(The customer seems to be concerned of noise emission related to internal clock.)

Best regards,

K.Hirano

All Replies

Posted by Kirby Kruckmeyer96848

on Apr 30 2012 21:19 PM

Intellectual800 points

Hello Kazuhiko,

I tried incorporating your questions with the answers, but I was having problems with the forum editor. So, here are just the answers:

Q1: Yes

Q2: Yes

Q3: Yes

Q4: tDOD would be the only factor. I have to investigate if we have these data.

Q5: Which comes first is random. It can be monitored through the DTM output. See page 43 for the register settings. This feature is not explained in detail in the datasheet.

Q6: This is correct, but I am investigating if there are more details we can provide.

Q7: I am investigating this one.

Q8: The VDD18 and DTM pins.

Q9 and Q10: It is best to bring them both up together, or the VDD33 first. There is no problem leaving the VDD33 powered up with no VDD18, but we would not recommend the other way around.

Q11: I am investigating.

Q12: The internal clock actually runs at 16x the INCLK. Other techniques are used to allow the 1/64 internal resolution.