The data sheet doesn't address this, and I can't find the answer elsewhere, so:
Simple question: If I am not using the internal PLL , can I drive the CLKIN input of the DAC5682Z with a non-symmetrical (<50% duty cycle) clock?
How fast is the
clock? At 1GSPS I wouldn’t recommend going beyond a 40/60% duty cycle. Below
800MSPS I wouldn't recommend going lower than 30/70% duty
I probably won't be going any faster than 800MHz, more likely we'll be running at about 600MHz. My problem is that I want to be able to adjust the sample rate and I need more resolution than just dividing my master clock by factors of two. From your comment can I assume that at lower frequencies the device can handle lower duty cycles? I would like to ASSUME that the device is synchronous with one edge or the other of the DCLK. Even if both edges of the clock are used internally , I would think that as long as setup/hold restraints are met, the device should work.
I guess I have some experimenting to do...
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